slackcoder/qemu - QEMU is a generic and open source machine & userspace emulator and virtualizer

Age	Commit message (Expand)	Author
2024-10-30	target/riscv: AMO operations always raise store/AMO fault	Deepak Gupta
2024-10-30	target/riscv: mmu changes for zicfiss shadow stack protection	Deepak Gupta
2024-10-30	target/riscv: tb flag for shadow stack instructions	Deepak Gupta
2024-10-30	target/riscv: introduce ssp and enabling controls for zicfiss	Deepak Gupta
2024-10-30	target/riscv: tracking indirect branches (fcfi) for zicfilp	Deepak Gupta
2024-10-30	target/riscv: additional code information for sw check	Deepak Gupta
2024-10-30	target/riscv: save and restore elp state on priv transitions	Deepak Gupta
2024-10-30	target/riscv: Correct mcause/scause bit width for RV32 in RV64 QEMU	TANG Tiancheng
2024-10-30	target/riscv: Detect sxl to set bit width for RV32 in RV64	TANG Tiancheng
2024-10-02	target/riscv/cpu_helper: Fix linking problem with semihosting disabled	Thomas Huth
2024-10-02	target/riscv32: Fix masking of physical address	Andrew Jones
2024-07-18	target/riscv: Implement privilege mode filtering for cycle/instret	Atish Patra
2024-07-18	target/riscv: Combine set_mode and set_virt functions.	Rajnesh Kanwal
2024-06-04	Merge tag 'hw-misc-accel-20240604' of https://github.com/philmd/qemu into sta...	Richard Henderson
2024-06-04	target/riscv: Restrict riscv_cpu_do_interrupt() to sysemu	Philippe Mathieu-Daudé
2024-06-03	target/riscv: do not set mtval2 for non guest-page faults	Alexei Filippov
2024-06-03	target/riscv: prioritize pmp errors in raise_mmu_exception()	Daniel Henrique Barboza
2024-06-03	target/riscv: Add support for Zve32x extension	Jason Chien
2024-06-03	target/riscv/debug: set tval=pc in breakpoint exceptions	Daniel Henrique Barboza
2024-05-06	exec/cpu: Extract page-protection definitions to page-protection.h	Philippe Mathieu-Daudé
2024-03-22	target/riscv: Fix mode in riscv_tlb_fill	Irina Ryapolova
2024-03-08	target/riscv: Fix privilege mode of G-stage translation for debugging	Hiroaki Yamamoto
2024-03-08	target/riscv: Gate hardware A/D PTE bit updating	Andrew Jones
2024-02-09	target/riscv: change vext_get_vlmax() arguments	Daniel Henrique Barboza
2024-02-03	target/riscv: Replace cpu_mmu_index with riscv_env_mmu_index	Richard Henderson
2024-02-03	target/riscv: Rename riscv_cpu_mmu_index to riscv_env_mmu_index	Richard Henderson
2024-01-10	target/riscv: Don't adjust vscause for exceptions	Alistair Francis
2024-01-08	qemu/main-loop: rename QEMU_IOTHREAD_LOCK_GUARD to BQL_LOCK_GUARD	Stefan Hajnoczi
2023-11-22	target/riscv/cpu_helper.c: Fix mxr bit behavior	Ivan Klokov
2023-11-22	target/riscv/cpu_helper.c: Invalid exception on MMU translation stage	Ivan Klokov
2023-11-07	target/riscv: Add HS-mode virtual interrupt and IRQ filtering support.	Rajnesh Kanwal
2023-11-07	target/riscv: Add M-mode virtual interrupt and IRQ filtering support.	Rajnesh Kanwal
2023-11-07	target/riscv: Split interrupt logic from riscv_cpu_update_mip.	Rajnesh Kanwal
2023-11-07	target/riscv: Check for async flag in case of RISCV_EXCP_SEMIHOST.	Rajnesh Kanwal
2023-10-12	target/riscv: Use env_archcpu for better performance	Richard W.M. Jones
2023-09-11	target/riscv: Update CSR bits name for svadu extension	Weiwei Li
2023-07-10	target/riscv: Set the correct exception for implict G-stage translation fail	Jason Chien
2023-07-10	target/riscv: update cur_pmbase/pmmask based on mode affected by MPRV	Weiwei Li
2023-07-10	target/riscv: Add additional xlen for address when MPRV=1	Weiwei Li
2023-07-10	target/riscv: Make MPV only work when MPP != PRV_M	Weiwei Li
2023-06-26	target: Widen pc/cs_base in cpu_get_tb_cpu_state	Anton Johansson
2023-06-13	target/riscv: Fix initialized value for cur_pmmask	Weiwei Li
2023-06-13	target/riscv: Reuse tb->flags.FS	Mayuresh Chitale
2023-06-13	target/riscv: Change the return type of pmp_hart_has_privs() to bool	Weiwei Li
2023-06-13	target/riscv: Move pmp_get_tlb_size apart from get_physical_address_pmp	Weiwei Li
2023-06-13	target/riscv: Update pmp_get_tlb_size()	Weiwei Li
2023-06-05	tcg: Split out tcg/oversized-guest.h	Richard Henderson
2023-05-05	riscv: Make sure an exception is raised if a pte is malformed	Alexandre Ghiti
2023-05-05	target/riscv: Fix Guest Physical Address Translation	Irina Ryapolova
2023-05-05	target/riscv: Reorg sum check in get_physical_address	Richard Henderson