slackcoder/qemu - QEMU is a generic and open source machine & userspace emulator and virtualizer

Age	Commit message (Expand)	Author
2024-11-07	target/riscv/kvm: Update kvm exts to Linux v6.11	Quan Zhou
2024-11-07	target/riscv: Inline unit-stride ld/st and corresponding functions for perfor...	Max Chou
2024-11-07	target/riscv: rvv: Provide group continuous ld/st flow for unit-stride ld/st ...	Max Chou
2024-11-07	target/riscv: rvv: Provide a fast path using direct access to host ram for un...	Max Chou
2024-11-07	target/riscv: rvv: Provide a fast path using direct access to host ram for un...	Max Chou
2024-11-07	target/riscv: rvv: Provide a fast path using direct access to host ram for un...	Max Chou
2024-11-07	target/riscv: rvv: Replace VSTART_CHECK_EARLY_EXIT in vext_ldst_us	Max Chou
2024-11-07	target/riscv: Set vdata.vm field for vector load/store whole register instruc...	Max Chou
2024-10-31	target/riscv: Fix vcompress with rvv_ta_all_1s	Anton Blanchard
2024-10-31	target/riscv/kvm: clarify how 'riscv-aia' default works	Daniel Henrique Barboza
2024-10-31	target/riscv/kvm: set 'aia_mode' to default in error path	Daniel Henrique Barboza
2024-10-31	target/riscv: Expose zicfiss extension as a cpu property	Deepak Gupta
2024-10-30	target/riscv: compressed encodings for sspush and sspopchk	Deepak Gupta
2024-10-30	target/riscv: implement zicfiss instructions	Deepak Gupta
2024-10-30	target/riscv: update `decode_save_opc` to store extra word2	Deepak Gupta
2024-10-30	target/riscv: AMO operations always raise store/AMO fault	Deepak Gupta
2024-10-30	target/riscv: mmu changes for zicfiss shadow stack protection	Deepak Gupta
2024-10-30	target/riscv: tb flag for shadow stack instructions	Deepak Gupta
2024-10-30	target/riscv: introduce ssp and enabling controls for zicfiss	Deepak Gupta
2024-10-30	target/riscv: Add zicfiss extension	Deepak Gupta
2024-10-30	target/riscv: Expose zicfilp extension as a cpu property	Deepak Gupta
2024-10-30	target/riscv: zicfilp `lpad` impl and branch tracking	Deepak Gupta
2024-10-30	target/riscv: tracking indirect branches (fcfi) for zicfilp	Deepak Gupta
2024-10-30	target/riscv: additional code information for sw check	Deepak Gupta
2024-10-30	target/riscv: save and restore elp state on priv transitions	Deepak Gupta
2024-10-30	target/riscv: Introduce elp state and enabling controls for zicfilp	Deepak Gupta
2024-10-30	target/riscv: Add zicfilp extension	Deepak Gupta
2024-10-30	target/riscv: expose *envcfg csr and priv to qemu-user as well	Deepak Gupta
2024-10-30	target/riscv: Set vtype.vill on CPU reset	Rob Bradford
2024-10-30	target/riscv: Add max32 CPU for RV64 QEMU	LIU Zhiwei
2024-10-30	target/riscv: Enable RV32 CPU support in RV64 QEMU	TANG Tiancheng
2024-10-30	target/riscv: Correct mcause/scause bit width for RV32 in RV64 QEMU	TANG Tiancheng
2024-10-30	target/riscv: Detect sxl to set bit width for RV32 in RV64	TANG Tiancheng
2024-10-30	target/riscv: Correct SXL return value for RV32 in RV64 QEMU	TANG Tiancheng
2024-10-30	target/riscv: Adjust PMP size for no-MMU RV64 QEMU running RV32	TANG Tiancheng
2024-10-30	target/riscv/csr.c: Fix an access to VXSAT	Evgenii Prokopiev
2024-10-04	Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging	Peter Maydell
2024-10-03	kvm: Allow kvm_arch_get/put_registers to accept Error**	Julia Suvorova
2024-10-02	target/riscv/cpu_helper: Fix linking problem with semihosting disabled	Thomas Huth
2024-10-02	target/riscv32: Fix masking of physical address	Andrew Jones
2024-10-02	target: riscv: Add Svvptc extension support	Alexandre Ghiti
2024-10-02	target/riscv: Add textra matching condition for the triggers	Alvin Chang
2024-10-02	target/riscv: Preliminary textra trigger CSR writting support	Alvin Chang
2024-10-02	target/riscv/cpu.c: Add 'fcsr' register to QEMU log as a part of F extension	Maria Klauchek
2024-10-02	target/riscv: Stop timer with infinite timecmp	Andrew Jones
2024-10-02	target/riscv/kvm: Fix the group bit setting of AIA	Andrew Jones
2024-10-02	target: riscv: Enable Bit Manip for OpenTitan Ibex CPU	Alistair Francis
2024-10-02	target/riscv: fix za64rs enabling	Vladimir Isaev
2024-10-02	target/riscv/tcg/tcg-cpu.c: consider MISA bit choice in implied rule	Daniel Henrique Barboza
2024-10-02	target/riscv: Add a property to set vl to ceil(AVL/2)	Jason Chien