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authorWeiwei Li <liweiwei@iscas.ac.cn>2023-06-14 11:25:47 +0800
committerAlistair Francis <alistair.francis@wdc.com>2023-07-10 22:29:14 +1000
commitef1ba32afff6b3d9be377804904b784da6594219 (patch)
treeddcfce6fcbcb2f00b9f5fecf4896ee056826aa61 /target/riscv/cpu_helper.c
parent3a610f5430f61bd67f0ac78ef40c8d3bd2b4f8ee (diff)
target/riscv: update cur_pmbase/pmmask based on mode affected by MPRV
Pointer mask is also affected by MPRV which means cur_pmbase/pmmask should also take MPRV into consideration. As pointer mask for instruction is not supported currently, so we can directly update cur_pmbase/pmmask based on address related mode and xlen affected by MPRV now. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-Id: <20230614032547.35895-3-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/cpu_helper.c')
-rw-r--r--target/riscv/cpu_helper.c7
1 files changed, 5 insertions, 2 deletions
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 2e771ddfc9..bb9d923818 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -149,13 +149,16 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
void riscv_cpu_update_mask(CPURISCVState *env)
{
target_ulong mask = 0, base = 0;
+ RISCVMXL xl = env->xl;
/*
* TODO: Current RVJ spec does not specify
* how the extension interacts with XLEN.
*/
#ifndef CONFIG_USER_ONLY
+ int mode = cpu_address_mode(env);
+ xl = cpu_get_xl(env, mode);
if (riscv_has_ext(env, RVJ)) {
- switch (env->priv) {
+ switch (mode) {
case PRV_M:
if (env->mmte & M_PM_ENABLE) {
mask = env->mpmmask;
@@ -179,7 +182,7 @@ void riscv_cpu_update_mask(CPURISCVState *env)
}
}
#endif
- if (env->xl == MXL_RV32) {
+ if (xl == MXL_RV32) {
env->cur_pmmask = mask & UINT32_MAX;
env->cur_pmbase = base & UINT32_MAX;
} else {