aboutsummaryrefslogtreecommitdiff
path: root/target/xtensa/overlay_tool.h
AgeCommit message (Expand)Author
2022-04-06Replace TARGET_WORDS_BIGENDIANMarc-André Lureau
2020-08-21target/xtensa: add DFPU registers and opcodesMax Filippov
2020-08-21target/xtensa: add DFPU optionMax Filippov
2020-08-21target/xtensa: implement NMI supportMax Filippov
2020-05-17target/xtensa: fetch HW version from configuration overlayMax Filippov
2020-01-06target/xtensa: use MPU background map from core configurationMax Filippov
2019-05-15target/xtensa: implement exclusive access optionMax Filippov
2019-05-14target/xtensa: implement DIWBUI.P opcodeMax Filippov
2019-05-10target/xtensa: implement MPU optionMax Filippov
2019-05-10target/xtensa: add parity/ECC option SRsMax Filippov
2019-05-10target/xtensa: define IDMA and gather/scatter IRQ typesMax Filippov
2019-02-18target/xtensa: move xtensa_finalize_config to xtensa_core_class_initMax Filippov
2019-01-11target/xtensa: rework zero overhead loops implementationMax Filippov
2018-06-30target/xtensa: check zero overhead loop alignmentMax Filippov
2018-03-13target/xtensa: use correct number of registers in gdbstubMax Filippov
2018-01-11target/xtensa: fix default sysrom/sysram addressesMax Filippov
2017-02-23target/xtensa: sim: instantiate local memoriesMax Filippov
2017-01-16target-xtensa: implement RER/WER instructionsMax Filippov
2017-01-15target/xtensa: implement MEMCTL SRMax Filippov
2017-01-15target/xtensa: fix ICACHE/DCACHE options detectionMax Filippov
2017-01-15target/xtensa: add static vectors selectionMax Filippov
2016-12-20Move target-* CPU file into a target/ folderThomas Huth