diff options
| author | Max Filippov <jcmvbkbc@gmail.com> | 2016-11-11 22:40:18 -0800 |
|---|---|---|
| committer | Max Filippov <jcmvbkbc@gmail.com> | 2017-01-15 13:01:56 -0800 |
| commit | 9e03ade4411c81a7f7d974dcedf0390835ce4096 (patch) | |
| tree | 5ed7163044ac610d041277e20def7990e507b1b5 /target/xtensa/overlay_tool.h | |
| parent | 4b37aaa879d508494df14bdc49830cdf8aa77a57 (diff) | |
target/xtensa: implement MEMCTL SR
MEMCTL SR controls zero overhead loop buffer and number of ways enabled
in L1 caches.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Diffstat (limited to 'target/xtensa/overlay_tool.h')
| -rw-r--r-- | target/xtensa/overlay_tool.h | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/target/xtensa/overlay_tool.h b/target/xtensa/overlay_tool.h index b73fd14dd1..bf36b5cdf6 100644 --- a/target/xtensa/overlay_tool.h +++ b/target/xtensa/overlay_tool.h @@ -59,6 +59,10 @@ #define XCHAL_HW_MIN_VERSION 0 #endif +#ifndef XCHAL_LOOP_BUFFER_SIZE +#define XCHAL_LOOP_BUFFER_SIZE 0 +#endif + #define XCHAL_OPTION(xchal, qemu) ((xchal) ? XTENSA_OPTION_BIT(qemu) : 0) #define XTENSA_OPTIONS ( \ @@ -343,6 +347,16 @@ .nibreak = XCHAL_NUM_IBREAK, \ .ndbreak = XCHAL_NUM_DBREAK +#define CACHE_SECTION \ + .icache_ways = XCHAL_ICACHE_WAYS, \ + .dcache_ways = XCHAL_DCACHE_WAYS, \ + .memctl_mask = \ + (XCHAL_ICACHE_SIZE ? MEMCTL_IUSEWAYS_MASK : 0) | \ + (XCHAL_DCACHE_SIZE ? \ + MEMCTL_DALLOCWAYS_MASK | MEMCTL_DUSEWAYS_MASK : 0) | \ + MEMCTL_ISNP | MEMCTL_DSNP | \ + (XCHAL_HAVE_LOOPS && XCHAL_LOOP_BUFFER_SIZE ? MEMCTL_IL0EN : 0) + #define CONFIG_SECTION \ .configid = { \ XCHAL_HW_CONFIGID0, \ @@ -357,6 +371,7 @@ INTERRUPTS_SECTION, \ TLB_SECTION, \ DEBUG_SECTION, \ + CACHE_SECTION, \ CONFIG_SECTION |