Age | Commit message (Expand) | Author |
2022-01-08 | target/riscv: accessors to registers upper part and 128-bit load/store | Frédéric Pétrot |
2021-05-11 | target/riscv: Consolidate RV32/64 16-bit instructions | Alistair Francis |
2019-05-24 | target/riscv: Add checks for several RVC reserved operands | Richard Henderson |
2019-05-24 | target/riscv: Split RVC32 and RVC64 insns into separate files | Richard Henderson |
2019-05-24 | target/riscv: Use pattern groups in insn16.decode | Richard Henderson |
2019-05-24 | target/riscv: Merge argument decode for RVC shifti | Richard Henderson |
2019-05-24 | target/riscv: Merge argument sets for insn32 and insn16 | Richard Henderson |
2019-03-13 | target/riscv: Convert quadrant 2 of RVXC insns to decodetree | Bastian Koppelmann |
2019-03-13 | target/riscv: Convert quadrant 1 of RVXC insns to decodetree | Bastian Koppelmann |
2019-03-13 | target/riscv: Convert quadrant 0 of RVXC insns to decodetree | Bastian Koppelmann |