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AgeCommit message (Expand)Author
2022-07-27RISC-V: Allow both Zmmul and MPalmer Dabbelt
2022-07-03target/riscv: Update default priority table for local interruptsAnup Patel
2022-07-03target/riscv: Remove CSRs that set/clear an IMSIC interrupt file bitsAnup Patel
2022-07-03target/riscv: Set minumum priv spec version for mcountinhibitAnup Patel
2022-07-03target/riscv: Don't force update priv spec version to latestAnup Patel
2022-07-03target/riscv: Ibex: Support priv version 1.11Alistair Francis
2022-07-03target/riscv: Fixup MSECCFG minimum priv checkAlistair Francis
2022-07-03target/riscv: Support mcycle/minstret write operationAtish Patra
2022-07-03target/riscv: Add support for hpmcounters/hpmeventsAtish Patra
2022-07-03target/riscv: Implement mcountinhibit CSRAtish Patra
2022-07-03target/riscv: pmu: Make number of counters configurableAtish Patra
2022-07-03target/riscv: pmu: Rename the counters extension to pmuAtish Patra
2022-07-03target/riscv: Implement PMU CSR predicate function for S-modeAtish Patra
2022-07-03target/riscv: Fix PMU CSR predicate functionAtish Patra
2022-07-03target/riscv/pmp: guard against PMP ranges with a negative sizeNicolas Pitre
2022-07-03target/riscv: Minimize the calls to decode_save_opcRichard Henderson
2022-07-03target/riscv: Remove generate_exception_mtvalRichard Henderson
2022-07-03target/riscv: Set env->bins in gen_exception_illegalRichard Henderson
2022-07-03target/riscv: Remove condition guarding register zero for auipc and luiVíctor Colombo
2022-06-28semihosting: Split out common-semi-target.hRichard Henderson
2022-06-28semihosting: Return void from do_common_semihostingRichard Henderson
2022-06-10target/riscv: trans_rvv: Avoid assert for RV32 and e64Alistair Francis
2022-06-10target/riscv: Don't expose the CPU properties on names CPUsAlistair Francis
2022-06-10target/riscv: rvv: Add option 'rvv_ta_all_1s' to enable optional tail agnosti...eopXD
2022-06-10target/riscv: rvv: Add tail agnostic for vector permutation instructionseopXD
2022-06-10target/riscv: rvv: Add tail agnostic for vector mask instructionseopXD
2022-06-10target/riscv: rvv: Add tail agnostic for vector reduction instructionseopXD
2022-06-10target/riscv: rvv: Add tail agnostic for vector floating-point instructionseopXD
2022-06-10target/riscv: rvv: Add tail agnostic for vector fix-point arithmetic instruct...eopXD
2022-06-10target/riscv: rvv: Add tail agnostic for vector integer merge and move instru...eopXD
2022-06-10target/riscv: rvv: Add tail agnostic for vector integer comparison instructionseopXD
2022-06-10target/riscv: rvv: Add tail agnostic for vector integer shift instructionseopXD
2022-06-10target/riscv: rvv: Add tail agnostic for vx, vvm, vxm instructionseopXD
2022-06-10target/riscv: rvv: Add tail agnostic for vector load / store instructionseopXD
2022-06-10target/riscv: rvv: Add tail agnostic for vv instructionseopXD
2022-06-10target/riscv: rvv: Early exit when vstart >= vleopXD
2022-06-10target/riscv: rvv: Rename ambiguous eszeopXD
2022-06-10target/riscv: rvv: Prune redundant access_type parameter passedeopXD
2022-06-10target/riscv: rvv: Prune redundant ESZ, DSZ parameter passedeopXD
2022-06-10target/riscv/debug.c: keep experimental rv128 support workingFrédéric Pétrot
2022-06-10target/riscv: Wake on VS-level external interruptsAndrew Bresticker
2022-06-10target/riscv: add support for zmmul extension v0.1Weiwei Li
2022-05-24target/riscv: add zicsr/zifencei to isa_stringHongren (Zenithal) Zheng
2022-05-24target/riscv: Set [m|s]tval for both illegal and virtual instruction trapsAnup Patel
2022-05-24target/riscv: Fix hstatus.GVA bit setting for traps taken from HS-modeAnup Patel
2022-05-24target/riscv: Fix csr number based privilege checkingAnup Patel
2022-05-24target/riscv: Fix typo of mimpid cpu optionFrank Chang
2022-05-24target/riscv: check 'I' and 'E' after checking 'G' in riscv_cpu_realizeWeiwei Li
2022-05-24target/riscv: Move/refactor ISA extension checksTsukasa OI
2022-05-24target/riscv: FP extension requirementsTsukasa OI
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