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QEMU is a generic and open source machine & userspace emulator and virtualizer
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riscv
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cpu_helper.c
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Commit message (
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Author
2023-06-05
tcg: Split out tcg/oversized-guest.h
Richard Henderson
2023-05-05
riscv: Make sure an exception is raised if a pte is malformed
Alexandre Ghiti
2023-05-05
target/riscv: Fix Guest Physical Address Translation
Irina Ryapolova
2023-05-05
target/riscv: Reorg sum check in get_physical_address
Richard Henderson
2023-05-05
target/riscv: Reorg access check in get_physical_address
Richard Henderson
2023-05-05
target/riscv: Merge checks for reserved pte flags
Richard Henderson
2023-05-05
target/riscv: Don't modify SUM with is_debug
Richard Henderson
2023-05-05
target/riscv: Suppress pte update with is_debug
Richard Henderson
2023-05-05
target/riscv: Move leaf pte processing out of level loop
Richard Henderson
2023-05-05
target/riscv: Hoist pbmte and hade out of the level loop
Richard Henderson
2023-05-05
target/riscv: Hoist second stage mode change to callers
Richard Henderson
2023-05-05
target/riscv: Check SUM in the correct register
Richard Henderson
2023-05-05
target/riscv: Set MMU_2STAGE_BIT in riscv_cpu_mmu_index
Richard Henderson
2023-05-05
target/riscv: Move hstatus.spvp check to check_access_hlsv
Richard Henderson
2023-05-05
target/riscv: Introduce mmuidx_2stage
Richard Henderson
2023-05-05
target/riscv: Introduce mmuidx_priv
Richard Henderson
2023-05-05
target/riscv: Introduce mmuidx_sum
Richard Henderson
2023-05-05
target/riscv: Rename MMU_HYP_ACCESS_BIT to MMU_2STAGE_BIT
Richard Henderson
2023-05-05
target/riscv: Handle HLV, HSV via helpers
Richard Henderson
2023-05-05
target/riscv: Reduce overhead of MSTATUS_SUM change
Fei Wu
2023-05-05
target/riscv: Separate priv from mmu_idx
Fei Wu
2023-05-05
target/riscv: Add a tb flags field for vstart
LIU Zhiwei
2023-05-05
target/riscv: Remove mstatus_hs_{fs, vs} from tb_flags
Richard Henderson
2023-05-05
target/riscv: Encode the FS and VS on a normal way for tb flags
LIU Zhiwei
2023-05-05
target/riscv: Extract virt enabled state from tb flags
LIU Zhiwei
2023-05-05
target/riscv: Legalize MPP value in write_mstatus
Weiwei Li
2023-05-05
target/riscv: Use PRV_RESERVED instead of PRV_H
Weiwei Li
2023-05-05
target/riscv: Fix lines with over 80 characters
Weiwei Li
2023-05-05
target/riscv: Fix format for comments
Weiwei Li
2023-05-05
target/riscv: Fix format for indentation
Weiwei Li
2023-05-05
target/riscv: Remove riscv_cpu_virt_enabled()
Weiwei Li
2023-05-05
target/riscv: Fix addr type for get_physical_address
Weiwei Li
2023-05-05
target/riscv: Remove redundant parentheses
Weiwei Li
2023-05-05
target/riscv: Convert env->virt to a bool env->virt_enabled
LIU Zhiwei
2023-05-05
target/riscv: Remove check on RVH for riscv_cpu_set_virt_enabled
Weiwei Li
2023-05-05
target/riscv: Remove check on RVH for riscv_cpu_virt_enabled
Weiwei Li
2023-05-05
target/riscv: Remove redundant call to riscv_cpu_virt_enabled
Weiwei Li
2023-05-05
target/riscv: Simplify type conversion for CPURISCVState
Weiwei Li
2023-05-05
target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig
Weiwei Li
2023-03-01
Merge patch series "target/riscv: Add support for Svadu extension"
Palmer Dabbelt
2023-03-01
target/riscv: Add *envcfg.HADE related check in address translation
Weiwei Li
2023-03-01
target/riscv: Add *envcfg.PBMTE related check in address translation
Weiwei Li
2023-03-01
Merge patch series "target/riscv: Some updates to float point related extensi...
Palmer Dabbelt
2023-03-01
target/riscv: Simplify check for Zve32f and Zve64f
Weiwei Li
2023-03-01
target/riscv: remove RISCV_FEATURE_MMU
Daniel Henrique Barboza
2023-03-01
target/riscv: remove RISCV_FEATURE_PMP
Daniel Henrique Barboza
2023-03-01
target/riscv: remove RISCV_FEATURE_DEBUG
Daniel Henrique Barboza
2023-02-23
target/riscv: avoid env_archcpu() in cpu_get_tb_cpu_state()
Daniel Henrique Barboza
2023-02-07
target/riscv: set tval for triggered watchpoints
Sergey Matyukevich
2023-02-07
target/riscv: Don't clear mask in riscv_cpu_update_mip() for VSTIP
Anup Patel
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