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-rw-r--r--tests/tcg/riscv64/semicall.h22
1 files changed, 22 insertions, 0 deletions
diff --git a/tests/tcg/riscv64/semicall.h b/tests/tcg/riscv64/semicall.h
new file mode 100644
index 0000000000..f8c88f32dc
--- /dev/null
+++ b/tests/tcg/riscv64/semicall.h
@@ -0,0 +1,22 @@
+/*
+ * Semihosting Tests - RiscV64 Helper
+ *
+ * Copyright (c) 2021
+ * Written by Alex Bennée <alex.bennee@linaro.org>
+ *
+ * SPDX-License-Identifier: GPL-3.0-or-later
+ */
+
+uintptr_t __semi_call(uintptr_t type, uintptr_t arg0)
+{
+ register uintptr_t t asm("a0") = type;
+ register uintptr_t a0 asm("a1") = arg0;
+ asm(".option norvc\n\t"
+ ".balign 16\n\t"
+ "slli zero, zero, 0x1f\n\t"
+ "ebreak\n\t"
+ "srai zero, zero, 0x7\n\t"
+ : "=r" (t)
+ : "r" (t), "r" (a0));
+ return t;
+}