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-rw-r--r--target/mips/cpu.h6
-rw-r--r--target/mips/internal.h1
-rw-r--r--target/mips/sysemu/machine.c4
-rw-r--r--target/mips/tcg/sysemu/cp0_helper.c63
-rw-r--r--target/mips/tcg/sysemu_helper.h.inc6
-rw-r--r--target/mips/tcg/translate.c62
-rw-r--r--target/mips/tcg/translate.h1
-rw-r--r--target/sparc/cpu.h5
-rw-r--r--target/sparc/helper.c16
-rw-r--r--target/sparc/helper.h1
-rw-r--r--target/sparc/translate.c13
11 files changed, 25 insertions, 153 deletions
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index ef26fe03c7..7329226d39 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -747,9 +747,7 @@ typedef struct CPUArchState {
* CP0 Register 9
*/
int32_t CP0_Count;
- uint32_t CP0_SAARI;
#define CP0SAARI_TARGET 0 /* 5..0 */
- uint64_t CP0_SAAR[2];
#define CP0SAAR_BASE 12 /* 43..12 */
#define CP0SAAR_SIZE 1 /* 5..1 */
#define CP0SAAR_EN 0
@@ -1174,7 +1172,6 @@ typedef struct CPUArchState {
uint32_t CP0_Status_rw_bitmask; /* Read/write bits in CP0_Status */
uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */
uint64_t insn_flags; /* Supported instruction set */
- int saarp;
/* Fields up to this point are cleared by a CPU reset */
struct {} end_reset_fields;
@@ -1183,8 +1180,7 @@ typedef struct CPUArchState {
CPUMIPSMVPContext *mvp;
#if !defined(CONFIG_USER_ONLY)
CPUMIPSTLBContext *tlb;
- void *irq[8];
- struct MIPSITUState *itu;
+ qemu_irq irq[8];
MemoryRegion *itc_tag; /* ITC Configuration Tags */
/* Loongson IOCSR memory */
diff --git a/target/mips/internal.h b/target/mips/internal.h
index 1d0c026c7d..a9a22ea00e 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -83,7 +83,6 @@ struct mips_def_t {
uint32_t lcsr_cpucfg2;
uint64_t insn_flags;
enum mips_mmu_types mmu_type;
- int32_t SAARP;
};
extern const char regnames[32][3];
diff --git a/target/mips/sysemu/machine.c b/target/mips/sysemu/machine.c
index 218f4c3a67..213fd637fc 100644
--- a/target/mips/sysemu/machine.c
+++ b/target/mips/sysemu/machine.c
@@ -281,8 +281,8 @@ const VMStateDescription vmstate_mips_cpu = {
VMSTATE_UINT32(env.CP0_BadInstrP, MIPSCPU),
VMSTATE_UINT32(env.CP0_BadInstrX, MIPSCPU),
VMSTATE_INT32(env.CP0_Count, MIPSCPU),
- VMSTATE_UINT32(env.CP0_SAARI, MIPSCPU),
- VMSTATE_UINT64_ARRAY(env.CP0_SAAR, MIPSCPU, 2),
+ VMSTATE_UNUSED(sizeof(uint32_t)), /* was CP0_SAARI */
+ VMSTATE_UNUSED(2 * sizeof(uint64_t)), /* was CP0_SAAR[2] */
VMSTATE_UINTTL(env.CP0_EntryHi, MIPSCPU),
VMSTATE_INT32(env.CP0_Compare, MIPSCPU),
VMSTATE_INT32(env.CP0_Status, MIPSCPU),
diff --git a/target/mips/tcg/sysemu/cp0_helper.c b/target/mips/tcg/sysemu/cp0_helper.c
index 62f6fb4bf6..ded6c78e9a 100644
--- a/target/mips/tcg/sysemu/cp0_helper.c
+++ b/target/mips/tcg/sysemu/cp0_helper.c
@@ -371,22 +371,6 @@ target_ulong helper_mfc0_count(CPUMIPSState *env)
return (int32_t)cpu_mips_get_count(env);
}
-target_ulong helper_mfc0_saar(CPUMIPSState *env)
-{
- if ((env->CP0_SAARI & 0x3f) < 2) {
- return (int32_t) env->CP0_SAAR[env->CP0_SAARI & 0x3f];
- }
- return 0;
-}
-
-target_ulong helper_mfhc0_saar(CPUMIPSState *env)
-{
- if ((env->CP0_SAARI & 0x3f) < 2) {
- return env->CP0_SAAR[env->CP0_SAARI & 0x3f] >> 32;
- }
- return 0;
-}
-
target_ulong helper_mftc0_entryhi(CPUMIPSState *env)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
@@ -514,13 +498,6 @@ target_ulong helper_dmfc0_watchhi(CPUMIPSState *env, uint32_t sel)
return env->CP0_WatchHi[sel];
}
-target_ulong helper_dmfc0_saar(CPUMIPSState *env)
-{
- if ((env->CP0_SAARI & 0x3f) < 2) {
- return env->CP0_SAAR[env->CP0_SAARI & 0x3f];
- }
- return 0;
-}
#endif /* TARGET_MIPS64 */
void helper_mtc0_index(CPUMIPSState *env, target_ulong arg1)
@@ -1100,46 +1077,6 @@ void helper_mtc0_count(CPUMIPSState *env, target_ulong arg1)
cpu_mips_store_count(env, arg1);
}
-void helper_mtc0_saari(CPUMIPSState *env, target_ulong arg1)
-{
- uint32_t target = arg1 & 0x3f;
- if (target <= 1) {
- env->CP0_SAARI = target;
- }
-}
-
-void helper_mtc0_saar(CPUMIPSState *env, target_ulong arg1)
-{
- uint32_t target = env->CP0_SAARI & 0x3f;
- if (target < 2) {
- env->CP0_SAAR[target] = arg1 & 0x00000ffffffff03fULL;
- switch (target) {
- case 0:
- if (env->itu) {
- itc_reconfigure(env->itu);
- }
- break;
- }
- }
-}
-
-void helper_mthc0_saar(CPUMIPSState *env, target_ulong arg1)
-{
- uint32_t target = env->CP0_SAARI & 0x3f;
- if (target < 2) {
- env->CP0_SAAR[target] =
- (((uint64_t) arg1 << 32) & 0x00000fff00000000ULL) |
- (env->CP0_SAAR[target] & 0x00000000ffffffffULL);
- switch (target) {
- case 0:
- if (env->itu) {
- itc_reconfigure(env->itu);
- }
- break;
- }
- }
-}
-
void helper_mtc0_entryhi(CPUMIPSState *env, target_ulong arg1)
{
target_ulong old, val, mask;
diff --git a/target/mips/tcg/sysemu_helper.h.inc b/target/mips/tcg/sysemu_helper.h.inc
index f163af1eac..1861d538de 100644
--- a/target/mips/tcg/sysemu_helper.h.inc
+++ b/target/mips/tcg/sysemu_helper.h.inc
@@ -31,8 +31,6 @@ DEF_HELPER_1(mftc0_tcschedule, tl, env)
DEF_HELPER_1(mfc0_tcschefback, tl, env)
DEF_HELPER_1(mftc0_tcschefback, tl, env)
DEF_HELPER_1(mfc0_count, tl, env)
-DEF_HELPER_1(mfc0_saar, tl, env)
-DEF_HELPER_1(mfhc0_saar, tl, env)
DEF_HELPER_1(mftc0_entryhi, tl, env)
DEF_HELPER_1(mftc0_status, tl, env)
DEF_HELPER_1(mftc0_cause, tl, env)
@@ -57,7 +55,6 @@ DEF_HELPER_1(dmfc0_lladdr, tl, env)
DEF_HELPER_1(dmfc0_maar, tl, env)
DEF_HELPER_2(dmfc0_watchlo, tl, env, i32)
DEF_HELPER_2(dmfc0_watchhi, tl, env, i32)
-DEF_HELPER_1(dmfc0_saar, tl, env)
#endif /* TARGET_MIPS64 */
DEF_HELPER_2(mtc0_index, void, env, tl)
@@ -103,9 +100,6 @@ DEF_HELPER_2(mtc0_srsconf4, void, env, tl)
DEF_HELPER_2(mtc0_hwrena, void, env, tl)
DEF_HELPER_2(mtc0_pwctl, void, env, tl)
DEF_HELPER_2(mtc0_count, void, env, tl)
-DEF_HELPER_2(mtc0_saari, void, env, tl)
-DEF_HELPER_2(mtc0_saar, void, env, tl)
-DEF_HELPER_2(mthc0_saar, void, env, tl)
DEF_HELPER_2(mtc0_entryhi, void, env, tl)
DEF_HELPER_2(mttc0_entryhi, void, env, tl)
DEF_HELPER_2(mtc0_compare, void, env, tl)
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index 12094cc1e7..3ba2101647 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/tcg/translate.c
@@ -5151,17 +5151,6 @@ static void gen_mfhc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CP0_REGISTER_09:
- switch (sel) {
- case CP0_REG09__SAAR:
- CP0_CHECK(ctx->saar);
- gen_helper_mfhc0_saar(arg, tcg_env);
- register_name = "SAAR";
- break;
- default:
- goto cp0_unimplemented;
- }
- break;
case CP0_REGISTER_17:
switch (sel) {
case CP0_REG17__LLADDR:
@@ -5252,17 +5241,6 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
- case CP0_REGISTER_09:
- switch (sel) {
- case CP0_REG09__SAAR:
- CP0_CHECK(ctx->saar);
- gen_helper_mthc0_saar(tcg_env, arg);
- register_name = "SAAR";
- break;
- default:
- goto cp0_unimplemented;
- }
- break;
case CP0_REGISTER_17:
switch (sel) {
case CP0_REG17__LLADDR:
@@ -5675,16 +5653,6 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
ctx->base.is_jmp = DISAS_EXIT;
register_name = "Count";
break;
- case CP0_REG09__SAARI:
- CP0_CHECK(ctx->saar);
- gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SAARI));
- register_name = "SAARI";
- break;
- case CP0_REG09__SAAR:
- CP0_CHECK(ctx->saar);
- gen_helper_mfc0_saar(arg, tcg_env);
- register_name = "SAAR";
- break;
default:
goto cp0_unimplemented;
}
@@ -6401,16 +6369,6 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
gen_helper_mtc0_count(tcg_env, arg);
register_name = "Count";
break;
- case CP0_REG09__SAARI:
- CP0_CHECK(ctx->saar);
- gen_helper_mtc0_saari(tcg_env, arg);
- register_name = "SAARI";
- break;
- case CP0_REG09__SAAR:
- CP0_CHECK(ctx->saar);
- gen_helper_mtc0_saar(tcg_env, arg);
- register_name = "SAAR";
- break;
default:
goto cp0_unimplemented;
}
@@ -7175,16 +7133,6 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
ctx->base.is_jmp = DISAS_EXIT;
register_name = "Count";
break;
- case CP0_REG09__SAARI:
- CP0_CHECK(ctx->saar);
- gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SAARI));
- register_name = "SAARI";
- break;
- case CP0_REG09__SAAR:
- CP0_CHECK(ctx->saar);
- gen_helper_dmfc0_saar(arg, tcg_env);
- register_name = "SAAR";
- break;
default:
goto cp0_unimplemented;
}
@@ -7887,16 +7835,6 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
gen_helper_mtc0_count(tcg_env, arg);
register_name = "Count";
break;
- case CP0_REG09__SAARI:
- CP0_CHECK(ctx->saar);
- gen_helper_mtc0_saari(tcg_env, arg);
- register_name = "SAARI";
- break;
- case CP0_REG09__SAAR:
- CP0_CHECK(ctx->saar);
- gen_helper_mtc0_saar(tcg_env, arg);
- register_name = "SAAR";
- break;
default:
goto cp0_unimplemented;
}
diff --git a/target/mips/tcg/translate.h b/target/mips/tcg/translate.h
index 93a78b8121..2b6646b339 100644
--- a/target/mips/tcg/translate.h
+++ b/target/mips/tcg/translate.h
@@ -49,7 +49,6 @@ typedef struct DisasContext {
bool mrp;
bool nan2008;
bool abs2008;
- bool saar;
bool mi;
int gi;
} DisasContext;
diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h
index edf46b387e..f3cdd17c62 100644
--- a/target/sparc/cpu.h
+++ b/target/sparc/cpu.h
@@ -545,10 +545,9 @@ struct CPUArchState {
#endif
sparc_def_t def;
- void *irq_manager;
+ /* Leon3 */
+ DeviceState *irq_manager;
void (*qemu_irq_ack)(CPUSPARCState *env, int intno);
-
- /* Leon3 cache control */
uint32_t cache_control;
};
diff --git a/target/sparc/helper.c b/target/sparc/helper.c
index bd10b60e4b..2247e243b5 100644
--- a/target/sparc/helper.c
+++ b/target/sparc/helper.c
@@ -212,4 +212,20 @@ void helper_power_down(CPUSPARCState *env)
env->npc = env->pc + 4;
cpu_loop_exit(cs);
}
+
+target_ulong helper_rdasr17(CPUSPARCState *env)
+{
+ CPUState *cs = env_cpu(env);
+ target_ulong val;
+
+ /*
+ * TODO: There are many more fields to be filled,
+ * some of which are writable.
+ */
+ val = env->def.nwindows - 1; /* [4:0] NWIN */
+ val |= 1 << 8; /* [8] V8 */
+ val |= (cs->cpu_index) << 28; /* [31:28] INDEX */
+
+ return val;
+}
#endif
diff --git a/target/sparc/helper.h b/target/sparc/helper.h
index 6a42ba4e9e..e55fad5b8c 100644
--- a/target/sparc/helper.h
+++ b/target/sparc/helper.h
@@ -2,6 +2,7 @@
DEF_HELPER_1(rett, void, env)
DEF_HELPER_2(wrpsr, void, env, tl)
DEF_HELPER_1(rdpsr, tl, env)
+DEF_HELPER_1(rdasr17, tl, env)
DEF_HELPER_1(power_down, void, env)
#else
DEF_HELPER_FLAGS_2(wrpil, TCG_CALL_NO_RWG, void, env, tl)
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index d9304a5bc4..692ce0b010 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -37,6 +37,7 @@
#ifdef TARGET_SPARC64
# define gen_helper_rdpsr(D, E) qemu_build_not_reached()
+# define gen_helper_rdasr17(D, E) qemu_build_not_reached()
# define gen_helper_rett(E) qemu_build_not_reached()
# define gen_helper_power_down(E) qemu_build_not_reached()
# define gen_helper_wrpsr(E, S) qemu_build_not_reached()
@@ -2382,16 +2383,8 @@ static bool trans_RDY(DisasContext *dc, arg_RDY *a)
static TCGv do_rd_leon3_config(DisasContext *dc, TCGv dst)
{
- uint32_t val;
-
- /*
- * TODO: There are many more fields to be filled,
- * some of which are writable.
- */
- val = dc->def->nwindows - 1; /* [4:0] NWIN */
- val |= 1 << 8; /* [8] V8 */
-
- return tcg_constant_tl(val);
+ gen_helper_rdasr17(dst, tcg_env);
+ return dst;
}
TRANS(RDASR17, ASR17, do_rd_special, true, a->rd, do_rd_leon3_config)
generated by cgit v1.2.3 (git 2.26.2) at 2025-03-22 11:22:37 +0000