diff options
| author | Richard Henderson <richard.henderson@linaro.org> | 2023-04-05 18:56:28 -0700 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2023-04-23 08:46:45 +0100 |
| commit | b9bfe000f954e1defefb4c917f98bf82c337144b (patch) | |
| tree | 681e36737e9a936a5c9a3213aa57c91b44478153 /tcg/riscv | |
| parent | 9c6aa274a494ce807e998a3652fa16a3d2da4387 (diff) | |
tcg: Split out tcg_out_extu_i32_i64
We will need a backend interface for type extension with zero.
Use it in tcg_reg_alloc_op in the meantime.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'tcg/riscv')
| -rw-r--r-- | tcg/riscv/tcg-target.c.inc | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 7bd3b421ad..064a334d82 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -607,6 +607,11 @@ static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg ret, TCGReg arg) tcg_out_ext32s(s, ret, arg); } +static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg ret, TCGReg arg) +{ + tcg_out_ext32u(s, ret, arg); +} + static void tcg_out_ldst(TCGContext *s, RISCVInsn opc, TCGReg data, TCGReg addr, intptr_t offset) { @@ -1602,10 +1607,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_qemu_st(s, args, true); break; - case INDEX_op_extu_i32_i64: - tcg_out_ext32u(s, a0, a1); - break; - case INDEX_op_extrl_i64_i32: tcg_out_ext32s(s, a0, a1); break; @@ -1644,6 +1645,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_ext32s_i64: case INDEX_op_ext32u_i64: case INDEX_op_ext_i32_i64: + case INDEX_op_extu_i32_i64: default: g_assert_not_reached(); } |