| Age | Commit message (Expand) | Author |
|---|
| 2024-10-22 | tcg/riscv: Enable native vector support for TCG host | TANG Tiancheng |
| 2024-10-22 | tcg/riscv: Implement vector roti/v/x ops | TANG Tiancheng |
| 2024-10-22 | tcg/riscv: Implement vector shi/s/v ops | TANG Tiancheng |
| 2024-10-22 | tcg/riscv: Implement vector min/max ops | TANG Tiancheng |
| 2024-10-22 | tcg/riscv: Implement vector sat/mul ops | TANG Tiancheng |
| 2024-10-22 | tcg/riscv: Accept constant first argument to sub_vec | Richard Henderson |
| 2024-10-22 | tcg/riscv: Implement vector neg ops | TANG Tiancheng |
| 2024-10-22 | tcg/riscv: Implement vector cmp/cmpsel ops | TANG Tiancheng |
| 2024-10-22 | tcg/riscv: Add support for basic vector opcodes | TANG Tiancheng |
| 2024-10-22 | tcg/riscv: Implement vector mov/dup{m/i} | TANG Tiancheng |
| 2024-10-22 | tcg/riscv: Add basic support for vector | Huang Shiyuan |
| 2024-07-03 | util/cpuinfo-riscv: Support host/cpuinfo.h for riscv | Richard Henderson |
| 2024-02-03 | tcg: Add TCGConst argument to tcg_target_const_match | Richard Henderson |
| 2024-02-03 | tcg: Introduce TCG_TARGET_HAS_tst | Richard Henderson |
| 2023-11-06 | tcg: Remove TCG_TARGET_HAS_neg_{i32,i64} | Richard Henderson |
| 2023-11-06 | tcg: Remove TCG_TARGET_HAS_movcond_{i32,i64} | Richard Henderson |
| 2023-10-22 | tcg/riscv: Use tcg_use_softmmu | Richard Henderson |
| 2023-10-22 | tcg/riscv: Do not reserve TCG_GUEST_BASE_REG for guest_base zero | Richard Henderson |
| 2023-10-07 | tcg: Correct invalid mentions of 'softmmu' by 'system-mode' | Philippe Mathieu-Daudé |
| 2023-09-16 | tcg: Add tcg_out_tb_start backend hook | Richard Henderson |
| 2023-09-15 | tcg: pass vece to tcg_target_const_match() | Jiajie Chen |
| 2023-08-24 | tcg: spelling fixes | Michael Tokarev |
| 2023-08-24 | tcg/riscv: Implement negsetcond_* | Richard Henderson |
| 2023-08-24 | tcg: Introduce negsetcond opcodes | Richard Henderson |
| 2023-08-24 | tcg: Unify TCG_TARGET_HAS_extr[lh]_i64_i32 | Richard Henderson |
| 2023-06-05 | tcg: Split out tcg-target-reg-bits.h | Richard Henderson |
| 2023-06-05 | tcg: Add tlb_fast_offset to TCGContext | Richard Henderson |
| 2023-06-05 | tcg: Widen CPUTLBEntry comparators to 64-bits | Richard Henderson |
| 2023-06-05 | tcg/riscv: Remove TARGET_LONG_BITS, TCG_TYPE_TL | Richard Henderson |
| 2023-05-30 | tcg: Remove TCG_TARGET_TLB_DISPLACEMENT_BITS | Richard Henderson |
| 2023-05-25 | tcg/riscv: Support CTZ, CLZ from Zbb | Richard Henderson |
| 2023-05-25 | tcg/riscv: Implement movcond | Richard Henderson |
| 2023-05-25 | tcg/riscv: Improve setcond expansion | Richard Henderson |
| 2023-05-25 | tcg/riscv: Support CPOP from Zbb | Richard Henderson |
| 2023-05-25 | tcg/riscv: Support REV8 from Zbb | Richard Henderson |
| 2023-05-25 | tcg/riscv: Support rotates from Zbb | Richard Henderson |
| 2023-05-25 | tcg/riscv: Use ADD.UW for guest address generation | Richard Henderson |
| 2023-05-25 | tcg/riscv: Support ADD.UW, SEXT.B, SEXT.H, ZEXT.H from Zba+Zbb | Richard Henderson |
| 2023-05-25 | tcg/riscv: Support ANDN, ORN, XNOR from Zbb | Richard Henderson |
| 2023-05-25 | tcg/riscv: Probe for Zba, Zbb, Zicond extensions | Richard Henderson |
| 2023-05-16 | tcg: Add page_bits and page_mask to TCGContext | Richard Henderson |
| 2023-05-16 | tcg: Split INDEX_op_qemu_{ld,st}* for guest address size | Richard Henderson |
| 2023-05-16 | tcg/riscv: Use atom_and_align_for_opc | Richard Henderson |
| 2023-05-16 | tcg: Add INDEX_op_qemu_{ld,st}_i128 | Richard Henderson |
| 2023-05-16 | tcg: Introduce tcg_target_has_memory_bswap | Richard Henderson |
| 2023-05-16 | tcg/riscv: Support softmmu unaligned accesses | Richard Henderson |
| 2023-05-16 | tcg/riscv: Use full load/store helpers in user-only mode | Richard Henderson |
| 2023-05-16 | tcg: Unify helper_{be,le}_{ld,st}* | Richard Henderson |
| 2023-05-11 | tcg/riscv: Simplify constraints on qemu_ld/st | Richard Henderson |
| 2023-05-11 | tcg/riscv: Convert tcg_out_qemu_{ld,st}_slow_path | Richard Henderson |
