diff options
| author | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2020-12-01 12:29:22 +0100 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2021-01-14 17:13:53 +0100 |
| commit | 8cd0b410a24159891809ba5f41fa55abb5adf196 (patch) | |
| tree | eebb4695edc7ab0d6edc156e017b13d75228b09a /hw/rtc | |
| parent | 7c79721606be11b5bc556449e5bcbc331ef6867d (diff) | |
target/mips: Add CP0 Config0 register definitions for MIPS3 ISA
The MIPS3 and MIPS32/64 ISA use different definitions
for the CP0 Config0 register.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201201132817.2863301-2-f4bug@amsat.org>
Diffstat (limited to 'hw/rtc')
0 files changed, 0 insertions, 0 deletions