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-rw-r--r--target/mips/cpu.h10
1 files changed, 9 insertions, 1 deletions
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 4cbc31c3e8..0086f95ea2 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -828,7 +828,7 @@ struct CPUMIPSState {
#define CP0EBase_WG 11
target_ulong CP0_CMGCRBase;
/*
- * CP0 Register 16
+ * CP0 Register 16 (after Release 1)
*/
int32_t CP0_Config0;
#define CP0C0_M 31
@@ -845,6 +845,14 @@ struct CPUMIPSState {
#define CP0C0_VI 3
#define CP0C0_K0 0 /* 2..0 */
#define CP0C0_AR_LENGTH 3
+/*
+ * CP0 Register 16 (before Release 1)
+ */
+#define CP0C0_Impl 16 /* 24..16 */
+#define CP0C0_IC 9 /* 11..9 */
+#define CP0C0_DC 6 /* 8..6 */
+#define CP0C0_IB 5
+#define CP0C0_DB 4
int32_t CP0_Config1;
#define CP0C1_M 31
#define CP0C1_MMU 25 /* 30..25 */