diff options
| author | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2020-12-02 18:53:20 +0100 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2020-12-13 20:26:02 +0100 |
| commit | ecc268e7c2488c0285684fad6d04cac6a794991d (patch) | |
| tree | 491e44e3466c5f7ff8e96ef24a4e00611d419c2c | |
| parent | 17c2c320f3c216f80c2fad1f0fa9358c2ffbd0d3 (diff) | |
target/mips: Do not initialize MT registers if MT ASE absent
Do not initialize MT-related config registers if the MT ASE
is not present. As some functions access the 'mvp' structure,
we still zero-allocate it.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201204222622.2743175-4-f4bug@amsat.org>
| -rw-r--r-- | target/mips/translate_init.c.inc | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/target/mips/translate_init.c.inc b/target/mips/translate_init.c.inc index 5a926bc6df..f72fee3b40 100644 --- a/target/mips/translate_init.c.inc +++ b/target/mips/translate_init.c.inc @@ -993,6 +993,10 @@ static void mvp_init(CPUMIPSState *env) { env->mvp = g_malloc0(sizeof(CPUMIPSMVPContext)); + if (!ase_mt_available(env)) { + return; + } + /* MVPConf1 implemented, TLB sharable, no gating storage support, programmable cache partitioning implemented, number of allocatable and shareable TLB entries, MVP has allocatable TCs, 2 VPEs |