aboutsummaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorGlenn Miles <milesg@linux.vnet.ibm.com>2024-09-13 11:16:49 -0500
committerNicholas Piggin <npiggin@gmail.com>2024-11-04 09:14:28 +1000
commitaa90c209bf672047947c1724b50a636a292b24b9 (patch)
tree152e977a0e113e86477acdcb3afb90305fccbec6
parentcebfeb9e56859bcac545a2340798e005cfde21cf (diff)
pnv/xive2: Support for "OS LGS Push" TIMA operation
Adds support for single byte writes to offset 0x15 of the TIMA address space. This offset holds the Logical Server Group Size (LGS) field. The field is used to evenly distribute the interrupt load among the members of a group, but is unused in the current implementation so we just support the writing of the value for now. Signed-off-by: Glenn Miles <milesg@linux.vnet.ibm.com> Signed-off-by: Michael Kowal <kowal@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
-rw-r--r--hw/intc/xive.c15
1 files changed, 15 insertions, 0 deletions
diff --git a/hw/intc/xive.c b/hw/intc/xive.c
index 4532cfc467..caa8dc74b6 100644
--- a/hw/intc/xive.c
+++ b/hw/intc/xive.c
@@ -341,6 +341,19 @@ static void xive_tm_set_os_cppr(XivePresenter *xptr, XiveTCTX *tctx,
xive_tctx_set_cppr(tctx, TM_QW1_OS, value & 0xff);
}
+static void xive_tctx_set_lgs(XiveTCTX *tctx, uint8_t ring, uint8_t lgs)
+{
+ uint8_t *regs = &tctx->regs[ring];
+
+ regs[TM_LGS] = lgs;
+}
+
+static void xive_tm_set_os_lgs(XivePresenter *xptr, XiveTCTX *tctx,
+ hwaddr offset, uint64_t value, unsigned size)
+{
+ xive_tctx_set_lgs(tctx, TM_QW1_OS, value & 0xff);
+}
+
/*
* Adjust the IPB to allow a CPU to process event queues of other
* priorities during one physical interrupt cycle.
@@ -525,6 +538,8 @@ static const XiveTmOp xive2_tm_operations[] = {
NULL },
{ XIVE_TM_HV_PAGE, TM_QW1_OS + TM_WORD2, 4, xive2_tm_push_os_ctx,
NULL },
+ { XIVE_TM_OS_PAGE, TM_QW1_OS + TM_LGS, 1, xive_tm_set_os_lgs,
+ NULL },
{ XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_CPPR, 1, xive_tm_set_hv_cppr,
NULL },
{ XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, xive_tm_vt_push,