From aa90c209bf672047947c1724b50a636a292b24b9 Mon Sep 17 00:00:00 2001 From: Glenn Miles Date: Fri, 13 Sep 2024 11:16:49 -0500 Subject: pnv/xive2: Support for "OS LGS Push" TIMA operation MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Adds support for single byte writes to offset 0x15 of the TIMA address space. This offset holds the Logical Server Group Size (LGS) field. The field is used to evenly distribute the interrupt load among the members of a group, but is unused in the current implementation so we just support the writing of the value for now. Signed-off-by: Glenn Miles Signed-off-by: Michael Kowal Reviewed-by: Cédric Le Goater Signed-off-by: Nicholas Piggin --- hw/intc/xive.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/hw/intc/xive.c b/hw/intc/xive.c index 4532cfc467..caa8dc74b6 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -341,6 +341,19 @@ static void xive_tm_set_os_cppr(XivePresenter *xptr, XiveTCTX *tctx, xive_tctx_set_cppr(tctx, TM_QW1_OS, value & 0xff); } +static void xive_tctx_set_lgs(XiveTCTX *tctx, uint8_t ring, uint8_t lgs) +{ + uint8_t *regs = &tctx->regs[ring]; + + regs[TM_LGS] = lgs; +} + +static void xive_tm_set_os_lgs(XivePresenter *xptr, XiveTCTX *tctx, + hwaddr offset, uint64_t value, unsigned size) +{ + xive_tctx_set_lgs(tctx, TM_QW1_OS, value & 0xff); +} + /* * Adjust the IPB to allow a CPU to process event queues of other * priorities during one physical interrupt cycle. @@ -525,6 +538,8 @@ static const XiveTmOp xive2_tm_operations[] = { NULL }, { XIVE_TM_HV_PAGE, TM_QW1_OS + TM_WORD2, 4, xive2_tm_push_os_ctx, NULL }, + { XIVE_TM_OS_PAGE, TM_QW1_OS + TM_LGS, 1, xive_tm_set_os_lgs, + NULL }, { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_CPPR, 1, xive_tm_set_hv_cppr, NULL }, { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, xive_tm_vt_push, -- cgit v1.2.3