diff options
| author | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2021-02-14 18:58:33 +0100 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2021-02-21 19:42:34 +0100 |
| commit | 9f5f7691dee18b0a0d6e0d8e291b7c12da85de17 (patch) | |
| tree | c08abdf906b212be1181724571eeda5a81bb4751 | |
| parent | 1e3b675b3e946f5c2b4b1aa96dc6413af8db9f04 (diff) | |
target/mips: Make cpu_HI/LO registers public
We will access the cpu_HI/LO registers outside of translate.c.
Make them publicly accessible.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210214175912.732946-4-f4bug@amsat.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
| -rw-r--r-- | target/mips/translate.c | 2 | ||||
| -rw-r--r-- | target/mips/translate.h | 1 |
2 files changed, 2 insertions, 1 deletions
diff --git a/target/mips/translate.c b/target/mips/translate.c index a6e835809a..c20f630b7e 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -2179,7 +2179,7 @@ enum { /* global register indices */ TCGv cpu_gpr[32], cpu_PC; -static TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC]; +TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC]; static TCGv cpu_dspctrl, btarget; TCGv bcond; static TCGv cpu_lladdr, cpu_llval; diff --git a/target/mips/translate.h b/target/mips/translate.h index f47b5f2c8d..2a1d8f570b 100644 --- a/target/mips/translate.h +++ b/target/mips/translate.h @@ -145,6 +145,7 @@ bool gen_lsa(DisasContext *ctx, int rd, int rt, int rs, int sa); bool gen_dlsa(DisasContext *ctx, int rd, int rt, int rs, int sa); extern TCGv cpu_gpr[32], cpu_PC; +extern TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC]; extern TCGv_i32 fpu_fcr0, fpu_fcr31; extern TCGv_i64 fpu_f64[32]; extern TCGv bcond; |