From 9f5f7691dee18b0a0d6e0d8e291b7c12da85de17 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Sun, 14 Feb 2021 18:58:33 +0100 Subject: target/mips: Make cpu_HI/LO registers public MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We will access the cpu_HI/LO registers outside of translate.c. Make them publicly accessible. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20210214175912.732946-4-f4bug@amsat.org> Signed-off-by: Philippe Mathieu-Daudé --- target/mips/translate.c | 2 +- target/mips/translate.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index a6e835809a..c20f630b7e 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -2179,7 +2179,7 @@ enum { /* global register indices */ TCGv cpu_gpr[32], cpu_PC; -static TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC]; +TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC]; static TCGv cpu_dspctrl, btarget; TCGv bcond; static TCGv cpu_lladdr, cpu_llval; diff --git a/target/mips/translate.h b/target/mips/translate.h index f47b5f2c8d..2a1d8f570b 100644 --- a/target/mips/translate.h +++ b/target/mips/translate.h @@ -145,6 +145,7 @@ bool gen_lsa(DisasContext *ctx, int rd, int rt, int rs, int sa); bool gen_dlsa(DisasContext *ctx, int rd, int rt, int rs, int sa); extern TCGv cpu_gpr[32], cpu_PC; +extern TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC]; extern TCGv_i32 fpu_fcr0, fpu_fcr31; extern TCGv_i64 fpu_f64[32]; extern TCGv bcond; -- cgit v1.2.3