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| author | William PC <w_calandrini[at]hotmail[dot]com> | 2022-11-05 05:36:42 +0000 |
|---|---|---|
| committer | Willy Sudiarto Raharjo <willysr@slackbuilds.org> | 2022-11-05 21:15:11 +0700 |
| commit | 66f5af0cd3942d3d7779d407fcebad4a0a2759be (patch) | |
| tree | bbf8b21dcc15cae1ba598d9b01663653f931109f /python/boolean-py/boolean-py.SlackBuild | |
| parent | a1d641657f265660dcdbfae2375aed2317dad80e (diff) | |
development/yosys: Added (A framework for Verilog RTL synthesis)
Signed-off-by: Willy Sudiarto Raharjo <willysr@slackbuilds.org>
Diffstat (limited to 'python/boolean-py/boolean-py.SlackBuild')
0 files changed, 0 insertions, 0 deletions