academic/verilog: Fix README.

Signed-off-by: B. Watson <yalhcru@gmail.com>

Signed-off-by: Willy Sudiarto Raharjo <willysr@slackbuilds.org>

1 files changed, 6 insertions, 5 deletions

diff --git a/academic/verilog/README b/academic/verilog/README
index c8ebda2ee7a57..9df78abc321a7 100644
--- a/academic/verilog/README
+++ b/academic/verilog/README
@@ -1,5 +1,6 @@
-Icarus Verilog is a Verilog simulation and synthesis tool.  It operates as
-a compiler, compiling source code written in Verilog (IEEE-1364) into some 
-target format.  For batch simulation, the compiler can generate an intermediate
-form called vvp assembly.  This intermediate form is executed by the 'vvp' 
-command.  For synthesis, the compiler generates netlists in the desired format.
+Icarus Verilog is a Verilog simulation and synthesis tool.  It operates
+as a compiler, compiling source code written in Verilog (IEEE-1364)
+into some target format.  For batch simulation, the compiler can
+generate an intermediate form called vvp assembly.  This intermediate
+form is executed by the 'vvp' command.  For synthesis, the compiler
+generates netlists in the desired format.