From 9a5f389f295820c8b18b7b11672c83db4a007d37 Mon Sep 17 00:00:00 2001 From: "B. Watson" Date: Mon, 12 Oct 2020 15:12:21 -0400 Subject: academic/verilog: Fix README. Signed-off-by: B. Watson Signed-off-by: Willy Sudiarto Raharjo --- academic/verilog/README | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) (limited to 'academic/verilog') diff --git a/academic/verilog/README b/academic/verilog/README index c8ebda2ee7..9df78abc32 100644 --- a/academic/verilog/README +++ b/academic/verilog/README @@ -1,5 +1,6 @@ -Icarus Verilog is a Verilog simulation and synthesis tool. It operates as -a compiler, compiling source code written in Verilog (IEEE-1364) into some -target format. For batch simulation, the compiler can generate an intermediate -form called vvp assembly. This intermediate form is executed by the 'vvp' -command. For synthesis, the compiler generates netlists in the desired format. +Icarus Verilog is a Verilog simulation and synthesis tool. It operates +as a compiler, compiling source code written in Verilog (IEEE-1364) +into some target format. For batch simulation, the compiler can +generate an intermediate form called vvp assembly. This intermediate +form is executed by the 'vvp' command. For synthesis, the compiler +generates netlists in the desired format. -- cgit v1.2.3