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/*
* STM32L4X5 RCC (Reset and clock control)
*
* Copyright (c) 2023 Arnaud Minier <arnaud.minier@telecom-paris.fr>
* Copyright (c) 2023 Inès Varhol <ines.varhol@telecom-paris.fr>
*
* SPDX-License-Identifier: GPL-2.0-or-later
*
* This work is licensed under the terms of the GNU GPL, version 2 or later.
* See the COPYING file in the top-level directory.
*
* The reference used is the STMicroElectronics RM0351 Reference manual
* for STM32L4x5 and STM32L4x6 advanced Arm ® -based 32-bit MCUs.
*
* Inspired by the BCM2835 CPRMAN clock manager implementation by Luc Michel.
*/
#ifndef HW_STM32L4X5_RCC_INTERNALS_H
#define HW_STM32L4X5_RCC_INTERNALS_H
#include "hw/registerfields.h"
#include "hw/misc/stm32l4x5_rcc.h"
#define TYPE_RCC_CLOCK_MUX "stm32l4x5-rcc-clock-mux"
#define TYPE_RCC_PLL "stm32l4x5-rcc-pll"
OBJECT_DECLARE_SIMPLE_TYPE(RccClockMuxState, RCC_CLOCK_MUX)
OBJECT_DECLARE_SIMPLE_TYPE(RccPllState, RCC_PLL)
/* Register map */
REG32(CR, 0x00)
FIELD(CR, PLLSAI2RDY, 29, 1)
FIELD(CR, PLLSAI2ON, 28, 1)
FIELD(CR, PLLSAI1RDY, 27, 1)
FIELD(CR, PLLSAI1ON, 26, 1)
FIELD(CR, PLLRDY, 25, 1)
FIELD(CR, PLLON, 24, 1)
FIELD(CR, CSSON, 19, 1)
FIELD(CR, HSEBYP, 18, 1)
FIELD(CR, HSERDY, 17, 1)
FIELD(CR, HSEON, 16, 1)
FIELD(CR, HSIASFS, 11, 1)
FIELD(CR, HSIRDY, 10, 1)
FIELD(CR, HSIKERON, 9, 1)
FIELD(CR, HSION, 8, 1)
FIELD(CR, MSIRANGE, 4, 4)
FIELD(CR, MSIRGSEL, 3, 1)
FIELD(CR, MSIPLLEN, 2, 1)
FIELD(CR, MSIRDY, 1, 1)
FIELD(CR, MSION, 0, 1)
REG32(ICSCR, 0x04)
FIELD(ICSCR, HSITRIM, 24, 7)
FIELD(ICSCR, HSICAL, 16, 8)
FIELD(ICSCR, MSITRIM, 8, 8)
FIELD(ICSCR, MSICAL, 0, 8)
REG32(CFGR, 0x08)
FIELD(CFGR, MCOPRE, 28, 3)
/* MCOSEL[2:0] only for STM32L475xx/476xx/486xx devices */
FIELD(CFGR, MCOSEL, 24, 3)
FIELD(CFGR, STOPWUCK, 15, 1)
FIELD(CFGR, PPRE2, 11, 3)
FIELD(CFGR, PPRE1, 8, 3)
FIELD(CFGR, HPRE, 4, 4)
FIELD(CFGR, SWS, 2, 2)
FIELD(CFGR, SW, 0, 2)
REG32(PLLCFGR, 0x0C)
FIELD(PLLCFGR, PLLPDIV, 27, 5)
FIELD(PLLCFGR, PLLR, 25, 2)
FIELD(PLLCFGR, PLLREN, 24, 1)
FIELD(PLLCFGR, PLLQ, 21, 2)
FIELD(PLLCFGR, PLLQEN, 20, 1)
FIELD(PLLCFGR, PLLP, 17, 1)
FIELD(PLLCFGR, PLLPEN, 16, 1)
FIELD(PLLCFGR, PLLN, 8, 7)
FIELD(PLLCFGR, PLLM, 4, 3)
FIELD(PLLCFGR, PLLSRC, 0, 2)
REG32(PLLSAI1CFGR, 0x10)
FIELD(PLLSAI1CFGR, PLLSAI1PDIV, 27, 5)
FIELD(PLLSAI1CFGR, PLLSAI1R, 25, 2)
FIELD(PLLSAI1CFGR, PLLSAI1REN, 24, 1)
FIELD(PLLSAI1CFGR, PLLSAI1Q, 21, 2)
FIELD(PLLSAI1CFGR, PLLSAI1QEN, 20, 1)
FIELD(PLLSAI1CFGR, PLLSAI1P, 17, 1)
FIELD(PLLSAI1CFGR, PLLSAI1PEN, 16, 1)
FIELD(PLLSAI1CFGR, PLLSAI1N, 8, 7)
REG32(PLLSAI2CFGR, 0x14)
FIELD(PLLSAI2CFGR, PLLSAI2PDIV, 27, 5)
FIELD(PLLSAI2CFGR, PLLSAI2R, 25, 2)
FIELD(PLLSAI2CFGR, PLLSAI2REN, 24, 1)
FIELD(PLLSAI2CFGR, PLLSAI2Q, 21, 2)
FIELD(PLLSAI2CFGR, PLLSAI2QEN, 20, 1)
FIELD(PLLSAI2CFGR, PLLSAI2P, 17, 1)
FIELD(PLLSAI2CFGR, PLLSAI2PEN, 16, 1)
FIELD(PLLSAI2CFGR, PLLSAI2N, 8, 7)
REG32(CIER, 0x18)
/* HSI48RDYIE: only on STM32L496xx/4A6xx devices */
FIELD(CIER, LSECSSIE, 9, 1)
FIELD(CIER, PLLSAI2RDYIE, 7, 1)
FIELD(CIER, PLLSAI1RDYIE, 6, 1)
FIELD(CIER, PLLRDYIE, 5, 1)
FIELD(CIER, HSERDYIE, 4, 1)
FIELD(CIER, HSIRDYIE, 3, 1)
FIELD(CIER, MSIRDYIE, 2, 1)
FIELD(CIER, LSERDYIE, 1, 1)
FIELD(CIER, LSIRDYIE, 0, 1)
REG32(CIFR, 0x1C)
/* HSI48RDYF: only on STM32L496xx/4A6xx devices */
FIELD(CIFR, LSECSSF, 9, 1)
FIELD(CIFR, CSSF, 8, 1)
FIELD(CIFR, PLLSAI2RDYF, 7, 1)
FIELD(CIFR, PLLSAI1RDYF, 6, 1)
FIELD(CIFR, PLLRDYF, 5, 1)
FIELD(CIFR, HSERDYF, 4, 1)
FIELD(CIFR, HSIRDYF, 3, 1)
FIELD(CIFR, MSIRDYF, 2, 1)
FIELD(CIFR, LSERDYF, 1, 1)
FIELD(CIFR, LSIRDYF, 0, 1)
REG32(CICR, 0x20)
/* HSI48RDYC: only on STM32L496xx/4A6xx devices */
FIELD(CICR, LSECSSC, 9, 1)
FIELD(CICR, CSSC, 8, 1)
FIELD(CICR, PLLSAI2RDYC, 7, 1)
FIELD(CICR, PLLSAI1RDYC, 6, 1)
FIELD(CICR, PLLRDYC, 5, 1)
FIELD(CICR, HSERDYC, 4, 1)
FIELD(CICR, HSIRDYC, 3, 1)
FIELD(CICR, MSIRDYC, 2, 1)
FIELD(CICR, LSERDYC, 1, 1)
FIELD(CICR, LSIRDYC, 0, 1)
REG32(AHB1RSTR, 0x28)
REG32(AHB2RSTR, 0x2C)
REG32(AHB3RSTR, 0x30)
REG32(APB1RSTR1, 0x38)
REG32(APB1RSTR2, 0x3C)
REG32(APB2RSTR, 0x40)
REG32(AHB1ENR, 0x48)
/* DMA2DEN: reserved for STM32L475xx */
FIELD(AHB1ENR, TSCEN, 16, 1)
FIELD(AHB1ENR, CRCEN, 12, 1)
FIELD(AHB1ENR, FLASHEN, 8, 1)
FIELD(AHB1ENR, DMA2EN, 1, 1)
FIELD(AHB1ENR, DMA1EN, 0, 1)
REG32(AHB2ENR, 0x4C)
FIELD(AHB2ENR, RNGEN, 18, 1)
/* HASHEN: reserved for STM32L475xx */
FIELD(AHB2ENR, AESEN, 16, 1)
/* DCMIEN: reserved for STM32L475xx */
FIELD(AHB2ENR, ADCEN, 13, 1)
FIELD(AHB2ENR, OTGFSEN, 12, 1)
/* GPIOIEN: reserved for STM32L475xx */
FIELD(AHB2ENR, GPIOHEN, 7, 1)
FIELD(AHB2ENR, GPIOGEN, 6, 1)
FIELD(AHB2ENR, GPIOFEN, 5, 1)
FIELD(AHB2ENR, GPIOEEN, 4, 1)
FIELD(AHB2ENR, GPIODEN, 3, 1)
FIELD(AHB2ENR, GPIOCEN, 2, 1)
FIELD(AHB2ENR, GPIOBEN, 1, 1)
FIELD(AHB2ENR, GPIOAEN, 0, 1)
REG32(AHB3ENR, 0x50)
FIELD(AHB3ENR, QSPIEN, 8, 1)
FIELD(AHB3ENR, FMCEN, 0, 1)
REG32(APB1ENR1, 0x58)
FIELD(APB1ENR1, LPTIM1EN, 31, 1)
FIELD(APB1ENR1, OPAMPEN, 30, 1)
FIELD(APB1ENR1, DAC1EN, 29, 1)
FIELD(APB1ENR1, PWREN, 28, 1)
FIELD(APB1ENR1, CAN2EN, 26, 1)
FIELD(APB1ENR1, CAN1EN, 25, 1)
/* CRSEN: reserved for STM32L475xx */
FIELD(APB1ENR1, I2C3EN, 23, 1)
FIELD(APB1ENR1, I2C2EN, 22, 1)
FIELD(APB1ENR1, I2C1EN, 21, 1)
FIELD(APB1ENR1, UART5EN, 20, 1)
FIELD(APB1ENR1, UART4EN, 19, 1)
FIELD(APB1ENR1, USART3EN, 18, 1)
FIELD(APB1ENR1, USART2EN, 17, 1)
FIELD(APB1ENR1, SPI3EN, 15, 1)
FIELD(APB1ENR1, SPI2EN, 14, 1)
FIELD(APB1ENR1, WWDGEN, 11, 1)
/* RTCAPBEN: reserved for STM32L475xx */
FIELD(APB1ENR1, LCDEN, 9, 1)
FIELD(APB1ENR1, TIM7EN, 5, 1)
FIELD(APB1ENR1, TIM6EN, 4, 1)
FIELD(APB1ENR1, TIM5EN, 3, 1)
FIELD(APB1ENR1, TIM4EN, 2, 1)
FIELD(APB1ENR1, TIM3EN, 1, 1)
FIELD(APB1ENR1, TIM2EN, 0, 1)
REG32(APB1ENR2, 0x5C)
FIELD(APB1ENR2, LPTIM2EN, 5, 1)
FIELD(APB1ENR2, SWPMI1EN, 2, 1)
/* I2C4EN: reserved for STM32L475xx */
FIELD(APB1ENR2, LPUART1EN, 0, 1)
REG32(APB2ENR, 0x60)
FIELD(APB2ENR, DFSDM1EN, 24, 1)
FIELD(APB2ENR, SAI2EN, 22, 1)
FIELD(APB2ENR, SAI1EN, 21, 1)
FIELD(APB2ENR, TIM17EN, 18, 1)
FIELD(APB2ENR, TIM16EN, 17, 1)
FIELD(APB2ENR, TIM15EN, 16, 1)
FIELD(APB2ENR, USART1EN, 14, 1)
FIELD(APB2ENR, TIM8EN, 13, 1)
FIELD(APB2ENR, SPI1EN, 12, 1)
FIELD(APB2ENR, TIM1EN, 11, 1)
FIELD(APB2ENR, SDMMC1EN, 10, 1)
FIELD(APB2ENR, FWEN, 7, 1)
FIELD(APB2ENR, SYSCFGEN, 0, 1)
REG32(AHB1SMENR, 0x68)
REG32(AHB2SMENR, 0x6C)
REG32(AHB3SMENR, 0x70)
REG32(APB1SMENR1, 0x78)
REG32(APB1SMENR2, 0x7C)
REG32(APB2SMENR, 0x80)
REG32(CCIPR, 0x88)
FIELD(CCIPR, DFSDM1SEL, 31, 1)
FIELD(CCIPR, SWPMI1SEL, 30, 1)
FIELD(CCIPR, ADCSEL, 28, 2)
FIELD(CCIPR, CLK48SEL, 26, 2)
FIELD(CCIPR, SAI2SEL, 24, 2)
FIELD(CCIPR, SAI1SEL, 22, 2)
FIELD(CCIPR, LPTIM2SEL, 20, 2)
FIELD(CCIPR, LPTIM1SEL, 18, 2)
FIELD(CCIPR, I2C3SEL, 16, 2)
FIELD(CCIPR, I2C2SEL, 14, 2)
FIELD(CCIPR, I2C1SEL, 12, 2)
FIELD(CCIPR, LPUART1SEL, 10, 2)
FIELD(CCIPR, UART5SEL, 8, 2)
FIELD(CCIPR, UART4SEL, 6, 2)
FIELD(CCIPR, USART3SEL, 4, 2)
FIELD(CCIPR, USART2SEL, 2, 2)
FIELD(CCIPR, USART1SEL, 0, 2)
REG32(BDCR, 0x90)
FIELD(BDCR, LSCOSEL, 25, 1)
FIELD(BDCR, LSCOEN, 24, 1)
FIELD(BDCR, BDRST, 16, 1)
FIELD(BDCR, RTCEN, 15, 1)
FIELD(BDCR, RTCSEL, 8, 2)
FIELD(BDCR, LSECSSD, 6, 1)
FIELD(BDCR, LSECSSON, 5, 1)
FIELD(BDCR, LSEDRV, 3, 2)
FIELD(BDCR, LSEBYP, 2, 1)
FIELD(BDCR, LSERDY, 1, 1)
FIELD(BDCR, LSEON, 0, 1)
REG32(CSR, 0x94)
FIELD(CSR, LPWRRSTF, 31, 1)
FIELD(CSR, WWDGRSTF, 30, 1)
FIELD(CSR, IWWGRSTF, 29, 1)
FIELD(CSR, SFTRSTF, 28, 1)
FIELD(CSR, BORRSTF, 27, 1)
FIELD(CSR, PINRSTF, 26, 1)
FIELD(CSR, OBLRSTF, 25, 1)
FIELD(CSR, FWRSTF, 24, 1)
FIELD(CSR, RMVF, 23, 1)
FIELD(CSR, MSISRANGE, 8, 4)
FIELD(CSR, LSIRDY, 1, 1)
FIELD(CSR, LSION, 0, 1)
/* CRRCR and CCIPR2 registers are present on L496/L4A6 devices only. */
/* Read Only masks to prevent writes in unauthorized bits */
#define CR_READ_ONLY_MASK (R_CR_PLLSAI2RDY_MASK | \
R_CR_PLLSAI1RDY_MASK | \
R_CR_PLLRDY_MASK | \
R_CR_HSERDY_MASK | \
R_CR_HSIRDY_MASK | \
R_CR_MSIRDY_MASK)
#define CR_READ_SET_MASK (R_CR_CSSON_MASK | R_CR_MSIRGSEL_MASK)
#define ICSCR_READ_ONLY_MASK (R_ICSCR_HSICAL_MASK | R_ICSCR_MSICAL_MASK)
#define CFGR_READ_ONLY_MASK (R_CFGR_SWS_MASK)
#define CIFR_READ_ONLY_MASK (R_CIFR_LSECSSF_MASK | \
R_CIFR_CSSF_MASK | \
R_CIFR_PLLSAI2RDYF_MASK | \
R_CIFR_PLLSAI1RDYF_MASK | \
R_CIFR_PLLRDYF_MASK | \
R_CIFR_HSERDYF_MASK | \
R_CIFR_HSIRDYF_MASK | \
R_CIFR_MSIRDYF_MASK | \
R_CIFR_LSERDYF_MASK | \
R_CIFR_LSIRDYF_MASK)
#define CIFR_IRQ_MASK CIFR_READ_ONLY_MASK
#define APB2ENR_READ_SET_MASK (R_APB2ENR_FWEN_MASK)
#define BDCR_READ_ONLY_MASK (R_BDCR_LSECSSD_MASK | R_BDCR_LSERDY_MASK)
#define CSR_READ_ONLY_MASK (R_CSR_LPWRRSTF_MASK | \
R_CSR_WWDGRSTF_MASK | \
R_CSR_IWWGRSTF_MASK | \
R_CSR_SFTRSTF_MASK | \
R_CSR_BORRSTF_MASK | \
R_CSR_PINRSTF_MASK | \
R_CSR_OBLRSTF_MASK | \
R_CSR_FWRSTF_MASK | \
R_CSR_LSIRDY_MASK)
/* Pll Channels */
enum PllChannels {
RCC_PLL_CHANNEL_PLLSAI3CLK = 0,
RCC_PLL_CHANNEL_PLL48M1CLK = 1,
RCC_PLL_CHANNEL_PLLCLK = 2,
};
enum PllSai1Channels {
RCC_PLLSAI1_CHANNEL_PLLSAI1CLK = 0,
RCC_PLLSAI1_CHANNEL_PLL48M2CLK = 1,
RCC_PLLSAI1_CHANNEL_PLLADC1CLK = 2,
};
enum PllSai2Channels {
RCC_PLLSAI2_CHANNEL_PLLSAI2CLK = 0,
/* No Q channel */
RCC_PLLSAI2_CHANNEL_PLLADC2CLK = 2,
};
typedef enum RccClockMuxSource {
RCC_CLOCK_MUX_SRC_GND = 0,
RCC_CLOCK_MUX_SRC_HSI,
RCC_CLOCK_MUX_SRC_HSE,
RCC_CLOCK_MUX_SRC_MSI,
RCC_CLOCK_MUX_SRC_LSI,
RCC_CLOCK_MUX_SRC_LSE,
RCC_CLOCK_MUX_SRC_SAI1_EXTCLK,
RCC_CLOCK_MUX_SRC_SAI2_EXTCLK,
RCC_CLOCK_MUX_SRC_PLL,
RCC_CLOCK_MUX_SRC_PLLSAI1,
RCC_CLOCK_MUX_SRC_PLLSAI2,
RCC_CLOCK_MUX_SRC_PLLSAI3,
RCC_CLOCK_MUX_SRC_PLL48M1,
RCC_CLOCK_MUX_SRC_PLL48M2,
RCC_CLOCK_MUX_SRC_PLLADC1,
RCC_CLOCK_MUX_SRC_PLLADC2,
RCC_CLOCK_MUX_SRC_SYSCLK,
RCC_CLOCK_MUX_SRC_HCLK,
RCC_CLOCK_MUX_SRC_PCLK1,
RCC_CLOCK_MUX_SRC_PCLK2,
RCC_CLOCK_MUX_SRC_HSE_OVER_32,
RCC_CLOCK_MUX_SRC_LCD_AND_RTC_COMMON,
RCC_CLOCK_MUX_SRC_NUMBER,
} RccClockMuxSource;
#endif /* HW_STM32L4X5_RCC_INTERNALS_H */
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