| Age | Commit message (Expand) | Author |
|---|
| 2024-02-03 | tcg: Add TCGConst argument to tcg_target_const_match | Richard Henderson |
| 2024-02-03 | tcg: Introduce TCG_TARGET_HAS_tst | Richard Henderson |
| 2024-02-03 | tcg/loongarch64: Set vector registers call clobbered | Richard Henderson |
| 2023-11-21 | tcg/loongarch64: Fix tcg_out_mov() Aborted | Song Gao |
| 2023-11-06 | tcg: Remove TCG_TARGET_HAS_neg_{i32,i64} | Richard Henderson |
| 2023-11-06 | tcg/loongarch64: Implement neg opcodes | Richard Henderson |
| 2023-11-06 | tcg: Remove TCG_TARGET_HAS_movcond_{i32,i64} | Richard Henderson |
| 2023-11-06 | tcg/loongarch64: Use cpuinfo.h | Richard Henderson |
| 2023-11-06 | tcg/loongarch64: Use C_N2_I1 for INDEX_op_qemu_ld_a*_i128 | Richard Henderson |
| 2023-10-22 | tcg/loongarch64: Use tcg_use_softmmu | Richard Henderson |
| 2023-10-07 | tcg: Correct invalid mentions of 'softmmu' by 'system-mode' | Philippe Mathieu-Daudé |
| 2023-10-04 | tcg/loongarch64: Fix buid error | gaosong |
| 2023-09-16 | tcg: Add tcg_out_tb_start backend hook | Richard Henderson |
| 2023-09-16 | tcg/loongarch64: Implement 128-bit load & store | Jiajie Chen |
| 2023-09-15 | tcg/loongarch64: Lower rotli_vec to vrotri | Jiajie Chen |
| 2023-09-15 | tcg/loongarch64: Lower rotv_vec ops to LSX | Jiajie Chen |
| 2023-09-15 | tcg/loongarch64: Lower vector shift integer ops | Jiajie Chen |
| 2023-09-15 | tcg/loongarch64: Lower bitsel_vec to vbitsel | Jiajie Chen |
| 2023-09-15 | tcg/loongarch64: Lower vector shift vector ops | Jiajie Chen |
| 2023-09-15 | tcg/loongarch64: Lower vector saturated ops | Jiajie Chen |
| 2023-09-15 | tcg/loongarch64: Lower vector min max ops | Jiajie Chen |
| 2023-09-15 | tcg/loongarch64: Lower mul_vec to vmul | Jiajie Chen |
| 2023-09-15 | tcg/loongarch64: Lower neg_vec to vneg | Jiajie Chen |
| 2023-09-15 | tcg/loongarch64: Lower vector bitwise operations | Jiajie Chen |
| 2023-09-15 | tcg/loongarch64: Lower add/sub_vec to vadd/vsub | Jiajie Chen |
| 2023-09-15 | tcg/loongarch64: Lower cmp_vec to vseq/vsle/vslt | Jiajie Chen |
| 2023-09-15 | tcg: pass vece to tcg_target_const_match() | Jiajie Chen |
| 2023-09-15 | tcg/loongarch64: Lower basic tcg vec ops to LSX | Jiajie Chen |
| 2023-09-15 | tcg/loongarch64: Import LSX instructions | Jiajie Chen |
| 2023-08-24 | tcg: Introduce negsetcond opcodes | Richard Henderson |
| 2023-08-24 | tcg: Unify TCG_TARGET_HAS_extr[lh]_i64_i32 | Richard Henderson |
| 2023-06-05 | tcg: Split out tcg-target-reg-bits.h | Richard Henderson |
| 2023-06-05 | tcg: Add tlb_fast_offset to TCGContext | Richard Henderson |
| 2023-06-05 | tcg: Widen CPUTLBEntry comparators to 64-bits | Richard Henderson |
| 2023-05-16 | tcg: Add page_bits and page_mask to TCGContext | Richard Henderson |
| 2023-05-16 | tcg/loongarch64: Remove TARGET_LONG_BITS, TCG_TYPE_TL | Richard Henderson |
| 2023-05-16 | tcg: Split INDEX_op_qemu_{ld,st}* for guest address size | Richard Henderson |
| 2023-05-16 | tcg/loongarch64: Use atom_and_align_for_opc | Richard Henderson |
| 2023-05-16 | tcg: Add INDEX_op_qemu_{ld,st}_i128 | Richard Henderson |
| 2023-05-16 | tcg: Introduce tcg_target_has_memory_bswap | Richard Henderson |
| 2023-05-16 | tcg/loongarch64: Support softmmu unaligned accesses | Richard Henderson |
| 2023-05-16 | tcg/loongarch64: Check the host supports unaligned accesses | Richard Henderson |
| 2023-05-16 | tcg/loongarch64: Use full load/store helpers in user-only mode | Richard Henderson |
| 2023-05-16 | tcg: Unify helper_{be,le}_{ld,st}* | Richard Henderson |
| 2023-05-11 | tcg/loongarch64: Simplify constraints on qemu_ld/st | Richard Henderson |
| 2023-05-11 | tcg/loongarch64: Convert tcg_out_qemu_{ld,st}_slow_path | Richard Henderson |
| 2023-05-11 | tcg/loongarch64: Introduce prepare_host_addr | Richard Henderson |
| 2023-05-05 | tcg/loongarch64: Introduce HostAddress | Richard Henderson |
| 2023-05-05 | tcg/loongarch64: Rationalize args to tcg_out_qemu_{ld,st} | Richard Henderson |
| 2023-05-02 | tcg/loongarch64: Conditionalize tcg_out_exts_i32_i64 | Richard Henderson |
