aboutsummaryrefslogtreecommitdiff
path: root/tcg/loongarch64/tcg-target-con-set.h
AgeCommit message (Expand)Author
2023-11-06tcg/loongarch64: Use C_N2_I1 for INDEX_op_qemu_ld_a*_i128Richard Henderson
2023-09-16tcg/loongarch64: Implement 128-bit load & storeJiajie Chen
2023-09-15tcg/loongarch64: Lower bitsel_vec to vbitselJiajie Chen
2023-09-15tcg/loongarch64: Lower vector bitwise operationsJiajie Chen
2023-09-15tcg/loongarch64: Lower add/sub_vec to vadd/vsubJiajie Chen
2023-09-15tcg/loongarch64: Lower cmp_vec to vseq/vsle/vsltJiajie Chen
2023-09-15tcg/loongarch64: Lower basic tcg vec ops to LSXJiajie Chen
2023-05-11tcg/loongarch64: Simplify constraints on qemu_ld/stRichard Henderson
2023-01-23tcg/loongarch64: Implement movcondRichard Henderson
2023-01-23tcg/loongarch64: Introduce tcg_out_addiRichard Henderson
2021-12-21tcg/loongarch64: Add softmmu load/store helpers, implement qemu_ld/qemu_st opsWANG Xuerui
2021-12-21tcg/loongarch64: Implement simple load/store opsWANG Xuerui
2021-12-21tcg/loongarch64: Implement setcond opsWANG Xuerui
2021-12-21tcg/loongarch64: Implement br/brcond opsWANG Xuerui
2021-12-21tcg/loongarch64: Implement mul/mulsh/muluh/div/divu/rem/remu opsWANG Xuerui
2021-12-21tcg/loongarch64: Implement add/sub opsWANG Xuerui
2021-12-21tcg/loongarch64: Implement shl/shr/sar/rotl/rotr opsWANG Xuerui
2021-12-21tcg/loongarch64: Implement clz/ctz opsWANG Xuerui
2021-12-21tcg/loongarch64: Implement deposit/extract opsWANG Xuerui
2021-12-21tcg/loongarch64: Implement not/and/or/xor/nor/andc/orc opsWANG Xuerui
2021-12-21tcg/loongarch64: Implement sign-/zero-extension opsWANG Xuerui
2021-12-21tcg/loongarch64: Implement goto_ptrWANG Xuerui