aboutsummaryrefslogtreecommitdiff
path: root/target/xtensa/translate.c
AgeCommit message (Expand)Author
2024-03-12target/xtensa: Prefer fast cpu_env() over slower CPU QOM cast macroPhilippe Mathieu-Daudé
2024-01-29target: Use vaddr in gen_intermediate_codeAnton Johansson
2024-01-19target/xtensa: use generic instruction breakpoint infrastructureMax Filippov
2023-10-22target/xtensa: Use tcg_gen_sextract_i32Richard Henderson
2023-10-04accel/tcg: Replace CPUState.env_ptr with cpu_env()Richard Henderson
2023-10-03tcg: Rename cpu_env to tcg_envRichard Henderson
2023-06-05accel/tcg: Introduce translator_io_startRichard Henderson
2023-06-05tcg: Pass TCGHelperInfo to tcg_gen_callNRichard Henderson
2023-05-05target/xtensa: Finish conversion to tcg_gen_qemu_{ld, st}_*Richard Henderson
2023-03-05target/xtensa: Avoid tcg_const_i32Richard Henderson
2023-03-05target/xtensa: Split constant in bit shiftRichard Henderson
2023-03-05target/xtensa: Use tcg_gen_subfi_i32 in translate_sllRichard Henderson
2023-03-05target/xtensa: Avoid tcg_const_i32 in translate_l32rRichard Henderson
2023-03-05target/xtensa: Tidy translate_clampsRichard Henderson
2023-03-05target/xtensa: Tidy translate_bbRichard Henderson
2023-03-05target/xtensa: Drop tcg_temp_freeRichard Henderson
2023-03-05target/xtensa: Drop reset_sar_trackerRichard Henderson
2023-03-01target/xtensa: Don't use tcg_temp_local_new_*Richard Henderson
2023-03-01accel/tcg: Pass max_insn to gen_intermediate_code by pointerRichard Henderson
2022-10-26target/xtensa: Convert to tcg_ops restore_state_to_opcRichard Henderson
2022-09-13target/xtensa: Honour -semihosting-config userspace=onPeter Maydell
2022-09-13semihosting: Allow optional use of semihosting from userspacePeter Maydell
2022-09-06accel/tcg: Add pc and host_pc params to gen_intermediate_codeRichard Henderson
2022-05-06target/xtensa: implement cache test option opcodesMax Filippov
2022-05-06target/xtensa: use tcg_constant_* for remaining opcodesMax Filippov
2022-05-06target/xtensa: use tcg_constant_* for FPU conversion opcodesMax Filippov
2022-05-06target/xtensa: use tcg_constant_* for numbered special registersMax Filippov
2022-05-06target/xtensa: use tcg_constant_* for TLB opcodesMax Filippov
2022-05-06target/xtensa: use tcg_constant_* for exceptionsMax Filippov
2022-05-06target/xtensa: use tcg_contatnt_* for numeric literalsMax Filippov
2022-05-06target/xtensa: fix missing tcg_temp_free in gen_window_checkMax Filippov
2022-04-20exec/translator: Pass the locked filepointer to disas_log hookRichard Henderson
2022-04-06Replace TARGET_WORDS_BIGENDIANMarc-André Lureau
2022-01-08exec/memop: Adding signedness to quad definitionsFrédéric Pétrot
2021-10-15target/xtensa: Drop check for singlestep_enabledRichard Henderson
2021-09-14accel/tcg: Add DisasContextBase argument to translator_ld*Ilya Leoshkevich
2021-07-21accel/tcg: Remove TranslatorOps.breakpoint_checkRichard Henderson
2021-07-09target/xtensa: Use translator_use_goto_tbRichard Henderson
2021-07-09tcg: Avoid including 'trace-tcg.h' in target translate.cPhilippe Mathieu-Daudé
2021-05-20target/xtensa: clean up unaligned accessMax Filippov
2021-05-20target/xtensa: fix access ring in l32exMax Filippov
2021-05-20target/xtensa: don't generate extra EXCP_DEBUG on exceptionMax Filippov
2021-05-20target/xtensa: Make sure that tb->size != 0Ilya Leoshkevich
2021-03-10semihosting: Move include/hw/semihosting/ -> include/semihosting/Philippe Mathieu-Daudé
2020-08-21target/xtensa: implement FPU division and square rootMax Filippov
2020-08-21target/xtensa: add DFPU registers and opcodesMax Filippov
2020-08-21target/xtensa: don't access BR regfile directlyMax Filippov
2020-08-21target/xtensa: move FSR/FCR register accessorsMax Filippov
2020-08-21target/xtensa: rename FPU2000 translators and helpersMax Filippov
2020-08-21target/xtensa: support copying registers up to 64 bits wideMax Filippov