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path: root/target/xtensa/translate.c
AgeCommit message (Expand)Author
2022-10-26target/xtensa: Convert to tcg_ops restore_state_to_opcRichard Henderson
2022-09-13target/xtensa: Honour -semihosting-config userspace=onPeter Maydell
2022-09-13semihosting: Allow optional use of semihosting from userspacePeter Maydell
2022-09-06accel/tcg: Add pc and host_pc params to gen_intermediate_codeRichard Henderson
2022-05-06target/xtensa: implement cache test option opcodesMax Filippov
2022-05-06target/xtensa: use tcg_constant_* for remaining opcodesMax Filippov
2022-05-06target/xtensa: use tcg_constant_* for FPU conversion opcodesMax Filippov
2022-05-06target/xtensa: use tcg_constant_* for numbered special registersMax Filippov
2022-05-06target/xtensa: use tcg_constant_* for TLB opcodesMax Filippov
2022-05-06target/xtensa: use tcg_constant_* for exceptionsMax Filippov
2022-05-06target/xtensa: use tcg_contatnt_* for numeric literalsMax Filippov
2022-05-06target/xtensa: fix missing tcg_temp_free in gen_window_checkMax Filippov
2022-04-20exec/translator: Pass the locked filepointer to disas_log hookRichard Henderson
2022-04-06Replace TARGET_WORDS_BIGENDIANMarc-André Lureau
2022-01-08exec/memop: Adding signedness to quad definitionsFrédéric Pétrot
2021-10-15target/xtensa: Drop check for singlestep_enabledRichard Henderson
2021-09-14accel/tcg: Add DisasContextBase argument to translator_ld*Ilya Leoshkevich
2021-07-21accel/tcg: Remove TranslatorOps.breakpoint_checkRichard Henderson
2021-07-09target/xtensa: Use translator_use_goto_tbRichard Henderson
2021-07-09tcg: Avoid including 'trace-tcg.h' in target translate.cPhilippe Mathieu-Daudé
2021-05-20target/xtensa: clean up unaligned accessMax Filippov
2021-05-20target/xtensa: fix access ring in l32exMax Filippov
2021-05-20target/xtensa: don't generate extra EXCP_DEBUG on exceptionMax Filippov
2021-05-20target/xtensa: Make sure that tb->size != 0Ilya Leoshkevich
2021-03-10semihosting: Move include/hw/semihosting/ -> include/semihosting/Philippe Mathieu-Daudé
2020-08-21target/xtensa: implement FPU division and square rootMax Filippov
2020-08-21target/xtensa: add DFPU registers and opcodesMax Filippov
2020-08-21target/xtensa: don't access BR regfile directlyMax Filippov
2020-08-21target/xtensa: move FSR/FCR register accessorsMax Filippov
2020-08-21target/xtensa: rename FPU2000 translators and helpersMax Filippov
2020-08-21target/xtensa: support copying registers up to 64 bits wideMax Filippov
2020-08-21target/xtensa: add geometry to xtensa_get_regfile_by_nameMax Filippov
2020-08-21target/xtensa: make opcode properties more dynamicMax Filippov
2020-06-22target/xtensa: drop gen_io_end callMax Filippov
2020-05-17target/xtensa: fix simcall for newer hardwareMax Filippov
2020-04-30target/xtensa: work around missing SR definitionsMax Filippov
2020-04-07target/xtensa: statically allocate xtensa_insnbufs in DisasContextMax Filippov
2020-04-07target/xtensa: fix pasto in pfwait.r opcode nameMax Filippov
2020-04-07target/xtensa: add FIXME for translation memory leakAlex Bennée
2020-01-15tcg: Search includes from the project root source directoryPhilippe Mathieu-Daudé
2020-01-06target/xtensa: fix ps.ring use in MPU configsMax Filippov
2019-10-28target/xtensa: fetch code with translator_ldEmilio G. Cota
2019-08-20icount: remove unnecessary gen_io_end callsPavel Dovgalyuk
2019-08-16Clean up inclusion of sysemu/sysemu.hMarkus Armbruster
2019-05-28semihosting: move semihosting configuration into its own directoryAlex Bennée
2019-05-21Merge remote-tracking branch 'remotes/xtensa/tags/20190520-xtensa' into stagingPeter Maydell
2019-05-15target/xtensa: implement exclusive access optionMax Filippov
2019-05-15target/xtensa: implement block prefetch option opcodesMax Filippov
2019-05-14target/xtensa: implement DIWBUI.P opcodeMax Filippov
2019-05-13target/xtensa: Use tcg_gen_abs_i32Richard Henderson