Age | Commit message (Expand) | Author |
---|---|---|
2017-02-23 | target/xtensa: sim: instantiate local memories | Max Filippov |
2017-01-16 | target-xtensa: implement RER/WER instructions | Max Filippov |
2017-01-15 | target/xtensa: implement MEMCTL SR | Max Filippov |
2017-01-15 | target/xtensa: fix ICACHE/DCACHE options detection | Max Filippov |
2017-01-15 | target/xtensa: add static vectors selection | Max Filippov |
2016-12-20 | Move target-* CPU file into a target/ folder | Thomas Huth |