| Age | Commit message (Expand) | Author |
|---|
| 2024-07-11 | target: Set TCGCPUOps::cpu_exec_halt to target's has_work implementation | Peter Maydell |
| 2024-06-19 | target/sparc: use signed denominator in sdiv helper | Clément Chigot |
| 2024-06-05 | target/sparc: Enable VIS4 feature bit | Richard Henderson |
| 2024-06-05 | target/sparc: Implement monitor ASIs | Richard Henderson |
| 2024-06-05 | target/sparc: Implement MWAIT | Richard Henderson |
| 2024-06-05 | target/sparc: Implement SUBXC, SUBXCcc | Richard Henderson |
| 2024-06-05 | target/sparc: Implement FPMIN, FPMAX | Richard Henderson |
| 2024-06-05 | target/sparc: Implement VIS4 comparisons | Richard Henderson |
| 2024-06-05 | target/sparc: Implement 8-bit FPADD, FPADDS, and FPADDUS | Richard Henderson |
| 2024-06-05 | target/sparc: Implement FALIGNDATAi | Richard Henderson |
| 2024-06-05 | target/sparc: Add feature bit for VIS4 | Richard Henderson |
| 2024-06-05 | target/sparc: Implement IMA extension | Richard Henderson |
| 2024-06-05 | target/sparc: Enable VIS3 feature bit | Richard Henderson |
| 2024-06-05 | target/sparc: Implement XMULX | Richard Henderson |
| 2024-06-05 | target/sparc: Implement UMULXHI | Richard Henderson |
| 2024-06-05 | target/sparc: Implement PDISTN | Richard Henderson |
| 2024-06-05 | target/sparc: Implement MOVsTOw, MOVdTOx, MOVwTOs, MOVxTOd | Richard Henderson |
| 2024-06-05 | target/sparc: Implement LZCNT | Richard Henderson |
| 2024-06-05 | target/sparc: Implement LDXEFSR | Richard Henderson |
| 2024-06-05 | target/sparc: Implement FSLL, FSRL, FSRA, FSLAS | Richard Henderson |
| 2024-06-05 | target/sparc: Implement FPCMPEQ8, FPCMPNE8, FPCMPULE8, FPCMPUGT8 | Richard Henderson |
| 2024-06-05 | target/sparc: Implement FPADDS, FPSUBS | Richard Henderson |
| 2024-06-05 | target/sparc: Implement FPADD64, FPSUB64 | Richard Henderson |
| 2024-06-05 | target/sparc: Implement FMEAN16 | Richard Henderson |
| 2024-06-05 | target/sparc: Implement FLCMP | Richard Henderson |
| 2024-06-05 | target/sparc: Implement FHADD, FHSUB, FNHADD, FNADD, FNMUL | Richard Henderson |
| 2024-06-05 | target/sparc: Implement FCHKSM16 | Richard Henderson |
| 2024-06-05 | target/sparc: Implement CMASK instructions | Richard Henderson |
| 2024-06-05 | target/sparc: Implement ADDXC, ADDXCcc | Richard Henderson |
| 2024-06-05 | target/sparc: Add feature bits for VIS 3 | Richard Henderson |
| 2024-06-05 | target/sparc: Implement FMAf extension | Richard Henderson |
| 2024-06-05 | target/sparc: Use gvec for VIS1 parallel add/sub | Richard Henderson |
| 2024-06-05 | target/sparc: Remove cpu_fpr[] | Richard Henderson |
| 2024-06-05 | target/sparc: Remove gen_dest_fpr_D | Richard Henderson |
| 2024-06-05 | target/sparc: Perform DFPREG/QFPREG in decodetree | Richard Henderson |
| 2024-06-05 | target/sparc: Fix helper_fmul8ulx16 | Richard Henderson |
| 2024-06-05 | target/sparc: Fix do_dc | Richard Henderson |
| 2024-06-05 | target/sparc: Rewrite gen_edge | Richard Henderson |
| 2024-06-05 | target/sparc: Fix ARRAY8 | Richard Henderson |
| 2024-05-15 | accel/tcg: Provide default implementation of disas_log | Richard Henderson |
| 2024-05-06 | Merge tag 'qemu-sparc-20240506' of https://github.com/mcayland/qemu into staging | Richard Henderson |
| 2024-05-06 | accel/tcg: Access tcg_cflags with getter / setter | Philippe Mathieu-Daudé |
| 2024-05-06 | exec/cpu: Extract page-protection definitions to page-protection.h | Philippe Mathieu-Daudé |
| 2024-05-05 | target/sparc: Split out do_ms16b | Richard Henderson |
| 2024-05-05 | target/sparc: Fix FPMERGE | Richard Henderson |
| 2024-05-05 | target/sparc: Fix FMULD8*X16 | Richard Henderson |
| 2024-05-05 | target/sparc: Fix FMUL8x16A{U,L} | Richard Henderson |
| 2024-05-05 | target/sparc: Fix FMUL8x16 | Richard Henderson |
| 2024-05-05 | target/sparc: Fix FEXPAND | Richard Henderson |
| 2024-05-05 | target/sparc/cpu: Avoid spaces by default in the CPU names | Thomas Huth |
