| Age | Commit message (Expand) | Author |
|---|
| 2024-06-05 | target/sparc: Implement FPCMPEQ8, FPCMPNE8, FPCMPULE8, FPCMPUGT8 | Richard Henderson |
| 2024-06-05 | target/sparc: Implement FPADDS, FPSUBS | Richard Henderson |
| 2024-06-05 | target/sparc: Implement FPADD64, FPSUB64 | Richard Henderson |
| 2024-06-05 | target/sparc: Implement FMEAN16 | Richard Henderson |
| 2024-06-05 | target/sparc: Implement FLCMP | Richard Henderson |
| 2024-06-05 | target/sparc: Implement FHADD, FHSUB, FNHADD, FNADD, FNMUL | Richard Henderson |
| 2024-06-05 | target/sparc: Implement FCHKSM16 | Richard Henderson |
| 2024-06-05 | target/sparc: Implement CMASK instructions | Richard Henderson |
| 2024-06-05 | target/sparc: Implement ADDXC, ADDXCcc | Richard Henderson |
| 2024-06-05 | target/sparc: Add feature bits for VIS 3 | Richard Henderson |
| 2024-06-05 | target/sparc: Implement FMAf extension | Richard Henderson |
| 2024-06-05 | target/sparc: Use gvec for VIS1 parallel add/sub | Richard Henderson |
| 2024-06-05 | target/sparc: Remove cpu_fpr[] | Richard Henderson |
| 2024-06-05 | target/sparc: Remove gen_dest_fpr_D | Richard Henderson |
| 2024-06-05 | target/sparc: Perform DFPREG/QFPREG in decodetree | Richard Henderson |
| 2024-06-05 | target/sparc: Fix do_dc | Richard Henderson |
| 2024-06-05 | target/sparc: Rewrite gen_edge | Richard Henderson |
| 2024-05-15 | accel/tcg: Provide default implementation of disas_log | Richard Henderson |
| 2024-05-05 | target/sparc: Fix FPMERGE | Richard Henderson |
| 2024-05-05 | target/sparc: Fix FMULD8*X16 | Richard Henderson |
| 2024-05-05 | target/sparc: Fix FMUL8x16A{U,L} | Richard Henderson |
| 2024-05-05 | target/sparc: Fix FMUL8x16 | Richard Henderson |
| 2024-05-05 | target/sparc: Fix FEXPAND | Richard Henderson |
| 2024-04-12 | target/sparc: Use GET_ASI_CODE for ASI_KERNELTXT and ASI_USERTXT | Richard Henderson |
| 2024-03-12 | target/sparc: Prefer fast cpu_env() over slower CPU QOM cast macro | Philippe Mathieu-Daudé |
| 2024-02-15 | target/sparc: implement asr17 feature for smp | Clément Chigot |
| 2024-02-03 | target/sparc: Use TCG_COND_TSTEQ in gen_op_mulscc | Richard Henderson |
| 2024-02-03 | target/sparc: Split fcc out of env->fsr | Richard Henderson |
| 2024-02-03 | target/sparc: Remove cpu_fsr | Richard Henderson |
| 2024-02-03 | target/sparc: Split cexc and ftt from env->fsr | Richard Henderson |
| 2024-02-03 | target/sparc: Merge check_ieee_exceptions with FPop helpers | Richard Henderson |
| 2024-02-03 | target/sparc: Clear cexc and ftt in do_check_ieee_exceptions | Richard Henderson |
| 2024-02-03 | target/sparc: Introduce cpu_get_fsr, cpu_put_fsr | Richard Henderson |
| 2024-02-03 | target/sparc: Use i128 for Fdmulq | Richard Henderson |
| 2024-02-03 | target/sparc: Use i128 for FdTOq, FxTOq | Richard Henderson |
| 2024-02-03 | target/sparc: Use i128 for FsTOq, FiTOq | Richard Henderson |
| 2024-02-03 | target/sparc: Use i128 for FCMPq, FCMPEq | Richard Henderson |
| 2024-02-03 | target/sparc: Use i128 for FqTOd, FqTOx | Richard Henderson |
| 2024-02-03 | target/sparc: Use i128 for FqTOs, FqTOi | Richard Henderson |
| 2024-02-03 | target/sparc: Use i128 for FADDq, FSUBq, FMULq, FDIVq | Richard Henderson |
| 2024-02-03 | target/sparc: Use i128 for FSQRTq | Richard Henderson |
| 2024-02-03 | target/sparc: Inline FNEG, FABS | Richard Henderson |
| 2024-02-03 | target/sparc: Introduce gen_{load,store}_fpr_Q | Richard Henderson |
| 2024-02-03 | target/sparc: Remove gen_dest_fpr_F | Richard Henderson |
| 2024-02-03 | target/sparc: Use tcg_gen_qemu_{ld, st}_i128 for ASI_M_BFILL | Richard Henderson |
| 2024-02-03 | target/sparc: Use tcg_gen_qemu_{ld, st}_i128 for ASI_M_BCOPY | Richard Henderson |
| 2024-01-29 | target: Use vaddr in gen_intermediate_code | Anton Johansson |
| 2023-11-14 | target/sparc: Fix RETURN | Richard Henderson |
| 2023-11-05 | target/sparc: Check for invalid cond in gen_compare_reg | Richard Henderson |
| 2023-11-05 | target/sparc: Implement UDIV inline | Richard Henderson |
