slackcoder/qemu - QEMU is a generic and open source machine & userspace emulator and virtualizer

Age	Commit message (Expand)	Author
2023-09-20	target/riscv/pmp.c: respect mseccfg.RLB for pmpaddrX changes	Leon Schuermann
2023-09-20	target/riscv: fix satp_mode_finalize() when satp_mode.supported = 0	Daniel Henrique Barboza
2023-09-10	kvm: Introduce kvm_arch_get_default_type hook	Akihiko Odaki
2023-05-10	target/riscv: Restore the predicate() NULL check behavior	Bin Meng
2023-05-10	target/riscv: Fix itrigger when icount is used	LIU Zhiwei
2023-03-13	target/riscv: Remove `NB_MMU_MODES` define	Anton Johansson
2023-03-07	gdbstub: move register helpers into standalone include	Alex Bennée
2023-03-07	includes: move tb_flush into its own header	Alex Bennée
2023-03-07	Merge tag 'pull-riscv-to-apply-20230306' of https://gitlab.com/palmer-dabbelt...	Peter Maydell
2023-03-06	riscv: Introduce satp mode hw capabilities	Alexandre Ghiti
2023-03-06	riscv: Allow user to set the satp mode	Alexandre Ghiti
2023-03-06	riscv: Change type of valid_vm_1_10_[32\|64] to bool	Alexandre Ghiti
2023-03-06	riscv: Pass Object to register_cpu_props instead of DeviceState	Alexandre Ghiti
2023-03-05	target/riscv: cpu: Implement get_arch_id callback	Mayuresh Chitale
2023-03-05	target/riscv: Avoid tcg_const_*	Richard Henderson
2023-03-05	target/riscv: Drop tcg_temp_free	Richard Henderson
2023-03-05	target/riscv: Drop temp_new	Richard Henderson
2023-03-05	target/riscv: Drop ftemp_new	Richard Henderson
2023-03-05	target/riscv: add Zicbop cbo.prefetch{i, r, m} placeholder	Christoph Muellner
2023-03-05	target/riscv: implement Zicbom extension	Christoph Muellner
2023-03-05	target/riscv: implement Zicboz extension	Christoph Muellner
2023-03-03	Merge tag 'pull-riscv-to-apply-20230303' of https://gitlab.com/palmer-dabbelt...	Peter Maydell
2023-03-01	Merge patch series "target/riscv: some vector_helper.c cleanups"	Palmer Dabbelt
2023-03-01	target/riscv/vector_helper.c: avoid env_archcpu() when reading RISCVCPUConfig	Daniel Henrique Barboza
2023-03-01	target/riscv/vector_helper.c: create vext_set_tail_elems_1s()	Daniel Henrique Barboza
2023-03-01	Merge patch series "RISCVCPUConfig related cleanups"	Palmer Dabbelt
2023-03-01	target/riscv/csr.c: avoid env_archcpu() usages when reading RISCVCPUConfig	Daniel Henrique Barboza
2023-03-01	target/riscv/csr.c: use riscv_cpu_cfg() to avoid env_cpu() pointers	Daniel Henrique Barboza
2023-03-01	target/riscv/csr.c: simplify mctr()	Daniel Henrique Barboza
2023-03-01	target/riscv/csr.c: use env_archcpu() in ctr()	Daniel Henrique Barboza
2023-03-01	Merge patch series "target/riscv: Add support for Svadu extension"	Palmer Dabbelt
2023-03-01	target/riscv: Export Svadu property	Weiwei Li
2023-03-01	target/riscv: Add *envcfg.HADE related check in address translation	Weiwei Li
2023-03-01	target/riscv: Add *envcfg.PBMTE related check in address translation	Weiwei Li
2023-03-01	target/riscv: Add csr support for svadu	Weiwei Li
2023-03-01	target/riscv: Fix the relationship of PBMTE/STCE fields between menvcfg and h...	Weiwei Li
2023-03-01	target/riscv: Fix the relationship between menvcfg.PBMTE/STCE and Svpbmt/Sstc...	Weiwei Li
2023-03-01	target/riscv: Add support for Zicond extension	Weiwei Li
2023-03-01	RISC-V: XTheadMemPair: Remove register restrictions for store-pair	Christoph Müllner
2023-03-01	target/riscv: Fix checking of whether instruciton at 'pc_next' spans pages	Shaobo Song
2023-03-01	Merge patch series "target/riscv: Various fixes to gdbstub and CSR access"	Palmer Dabbelt
2023-03-01	target/riscv: Group all predicate() routines together	Bin Meng
2023-03-01	target/riscv: Drop priv level check in mseccfg predicate()	Bin Meng
2023-03-01	target/riscv: Allow debugger to access sstc CSRs	Bin Meng
2023-03-01	target/riscv: Allow debugger to access {h, s}stateen CSRs	Bin Meng
2023-03-01	target/riscv: Allow debugger to access seed CSR	Bin Meng
2023-03-01	target/riscv: Allow debugger to access user timer and counter CSRs	Bin Meng
2023-03-01	target/riscv: gdbstub: Drop the vector CSRs in riscv-vector.xml	Bin Meng
2023-03-01	target/riscv: gdbstub: Turn on debugger mode before calling CSR predicate()	Bin Meng
2023-03-01	target/riscv: Avoid reporting odd-numbered pmpcfgX in the CSR XML for RV64	Bin Meng