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AgeCommit message (Expand)Author
2021-11-02target/riscv: Make riscv_cpu_tlb_fill sysemu onlyRichard Henderson
2021-10-29target/riscv: change the api for RVF/RVD fmin/fmaxChih-Min Chao
2021-10-29target/riscv: remove force HS exceptionJose Martins
2021-10-29target/riscv: fix VS interrupts forwarding to HSJose Martins
2021-10-28target/riscv: Allow experimental J-ext to be turned onAlexey Baturo
2021-10-28target/riscv: Implement address masking functions required for RISC-V Pointer...Anatoly Parshintsev
2021-10-28target/riscv: Support pointer masking for RISC-V for i/c/f/d/a types of instr...Alexey Baturo
2021-10-28target/riscv: Print new PM CSRs in QEMU logsAlexey Baturo
2021-10-28target/riscv: Add J extension state descriptionAlexey Baturo
2021-10-28target/riscv: Support CSRs required for RISC-V PM extension except for the h-...Alexey Baturo
2021-10-28target/riscv: Add CSR defines for RISC-V PM extensionAlexey Baturo
2021-10-28target/riscv: Add J-extension into RISC-VAlexey Baturo
2021-10-22target/riscv: Compute mstatus.sd on demandRichard Henderson
2021-10-22target/riscv: Use riscv_csrrw_debug for cpu_dumpRichard Henderson
2021-10-22target/riscv: Use gen_shift*_per_ol for RVB, RVIRichard Henderson
2021-10-22target/riscv: Use gen_unary_per_ol for RVBRichard Henderson
2021-10-22target/riscv: Adjust trans_rev8_32 for riscv64Richard Henderson
2021-10-22target/riscv: Use gen_arith_per_ol for RVMRichard Henderson
2021-10-22target/riscv: Replace DisasContext.w with DisasContext.olRichard Henderson
2021-10-22target/riscv: Replace is_32bit with get_xl/get_xlenRichard Henderson
2021-10-22target/riscv: Properly check SEW in amo_opRichard Henderson
2021-10-22target/riscv: Use REQUIRE_64BIT in amo_check64Richard Henderson
2021-10-22target/riscv: Add MXL/SXL/UXL to TB_FLAGSRichard Henderson
2021-10-22target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxlRichard Henderson
2021-10-22target/riscv: Split misa.mxl and misa.extRichard Henderson
2021-10-22target/riscv: Create RISCVMXL enumerationRichard Henderson
2021-10-22target/riscv: Move cpu_get_tb_cpu_state out of lineRichard Henderson
2021-10-22target/riscv: Organise the CPU propertiesAlistair Francis
2021-10-22target/riscv: Remove some unused macrosAlistair Francis
2021-10-22target/riscv: fix TB_FLAGS bits overlapping bug for rvv/rvhFrank Chang
2021-10-22target/riscv: Fix orc.b implementationPhilipp Tomsich
2021-10-22target/riscv: line up all of the registers in the info register dumpTravis Geiselbrecht
2021-10-22target/riscv: Pass the same value to oprsz and maxsz for vmv.v.vFrank Chang
2021-10-15target/riscv: Remove exit_tb and lookup_and_goto_ptrRichard Henderson
2021-10-15target/riscv: Remove dead code after exceptionRichard Henderson
2021-10-07target/riscv: Set mstatus_hs.[SD|FS] bits if Clean and V=1 in mark_fs_dirty()Frank Chang
2021-10-07target/riscv: Remove RVB (replaced by Zb[abcs])Philipp Tomsich
2021-10-07target/riscv: Add zext.h instructions to Zbb, removing pack/packu/packhPhilipp Tomsich
2021-10-07target/riscv: Add rev8 instruction, removing grev/greviPhilipp Tomsich
2021-10-07target/riscv: Add a REQUIRE_32BIT macroPhilipp Tomsich
2021-10-07target/riscv: Add orc.b instruction for Zbb, removing gorc/gorciPhilipp Tomsich
2021-10-07target/riscv: Reassign instructions to the Zbb-extensionPhilipp Tomsich
2021-10-07target/riscv: Add instructions of the Zbc-extensionPhilipp Tomsich
2021-10-07target/riscv: Reassign instructions to the Zbs-extensionPhilipp Tomsich
2021-10-07target/riscv: Remove shift-one instructions (proposed Zbo in pre-0.93 draft-B)Philipp Tomsich
2021-10-07target/riscv: Remove the W-form instructions from ZbsPhilipp Tomsich
2021-10-07target/riscv: Reassign instructions to the Zba-extensionPhilipp Tomsich
2021-10-07target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs propertiesPhilipp Tomsich
2021-10-07target/riscv: clwz must ignore high bits (use shift-left & changed logic)Philipp Tomsich
2021-10-07target/riscv: fix clzw implementation to operate on arg1Philipp Tomsich
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