Age | Commit message (Expand) | Author |
2023-03-01 | target/riscv/vector_helper.c: avoid env_archcpu() when reading RISCVCPUConfig | Daniel Henrique Barboza |
2023-03-01 | target/riscv/vector_helper.c: create vext_set_tail_elems_1s() | Daniel Henrique Barboza |
2023-02-23 | target/riscv: Fix vslide1up.vf and vslide1down.vf | LIU Zhiwei |
2022-12-14 | cleanup: Tweak and re-run return_directly.cocci | Markus Armbruster |
2022-10-24 | treewide: Remove the unnecessary space before semicolon | Bin Meng |
2022-09-27 | target/riscv: rvv-1.0: vf[w]redsum distinguish between ordered/unordered | Yang Liu |
2022-09-27 | target/riscv: rvv-1.0: Simplify vfwredsum code | Yang Liu |
2022-09-07 | target/riscv: rvv: Add mask agnostic for vector permutation instructions | Yueh-Ting (eop) Chen |
2022-09-07 | target/riscv: rvv: Add mask agnostic for vector mask instructions | Yueh-Ting (eop) Chen |
2022-09-07 | target/riscv: rvv: Add mask agnostic for vector floating-point instructions | Yueh-Ting (eop) Chen |
2022-09-07 | target/riscv: rvv: Add mask agnostic for vector fix-point arithmetic instruct... | Yueh-Ting (eop) Chen |
2022-09-07 | target/riscv: rvv: Add mask agnostic for vector integer comparison instructions | Yueh-Ting (eop) Chen |
2022-09-07 | target/riscv: rvv: Add mask agnostic for vector integer shift instructions | Yueh-Ting (eop) Chen |
2022-09-07 | target/riscv: rvv: Add mask agnostic for vx instructions | Yueh-Ting (eop) Chen |
2022-09-07 | target/riscv: rvv: Add mask agnostic for vector load / store instructions | Yueh-Ting (eop) Chen |
2022-09-07 | target/riscv: rvv: Add mask agnostic for vv instructions | Yueh-Ting (eop) Chen |
2022-06-10 | target/riscv: rvv: Add tail agnostic for vector permutation instructions | eopXD |
2022-06-10 | target/riscv: rvv: Add tail agnostic for vector mask instructions | eopXD |
2022-06-10 | target/riscv: rvv: Add tail agnostic for vector reduction instructions | eopXD |
2022-06-10 | target/riscv: rvv: Add tail agnostic for vector floating-point instructions | eopXD |
2022-06-10 | target/riscv: rvv: Add tail agnostic for vector fix-point arithmetic instruct... | eopXD |
2022-06-10 | target/riscv: rvv: Add tail agnostic for vector integer merge and move instru... | eopXD |
2022-06-10 | target/riscv: rvv: Add tail agnostic for vector integer comparison instructions | eopXD |
2022-06-10 | target/riscv: rvv: Add tail agnostic for vector integer shift instructions | eopXD |
2022-06-10 | target/riscv: rvv: Add tail agnostic for vx, vvm, vxm instructions | eopXD |
2022-06-10 | target/riscv: rvv: Add tail agnostic for vector load / store instructions | eopXD |
2022-06-10 | target/riscv: rvv: Add tail agnostic for vv instructions | eopXD |
2022-06-10 | target/riscv: rvv: Rename ambiguous esz | eopXD |
2022-06-10 | target/riscv: rvv: Prune redundant access_type parameter passed | eopXD |
2022-06-10 | target/riscv: rvv: Prune redundant ESZ, DSZ parameter passed | eopXD |
2022-04-22 | target/riscv: fix start byte for vmv<nf>r.v when vstart != 0 | Weiwei Li |
2022-04-22 | target/riscv: optimize helper for vmv<nr>r.v | Weiwei Li |
2022-04-06 | Replace config-time define HOST_WORDS_BIGENDIAN | Marc-André Lureau |
2022-02-16 | target/riscv: Fix vill field write in vtype | LIU Zhiwei |
2022-01-21 | target/riscv: Adjust vector address with mask | LIU Zhiwei |
2022-01-21 | target/riscv: Fix check range for first fault only | LIU Zhiwei |
2022-01-21 | target/riscv: Adjust vsetvl according to XLEN | LIU Zhiwei |
2022-01-21 | target/riscv: Split out the vill from vtype | LIU Zhiwei |
2021-12-20 | target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to vmandn.mm and vmo... | Frank Chang |
2021-12-20 | target/riscv: rvv-1.0: add vector unit-stride mask load/store insns | Frank Chang |
2021-12-20 | target/riscv: rvv-1.0: add evl parameter to vext_ldst_us() | Frank Chang |
2021-12-20 | target/riscv: rvv-1.0: floating-point reciprocal estimate instruction | Frank Chang |
2021-12-20 | target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruc... | Frank Chang |
2021-12-20 | target/riscv: rvv-1.0: implement vstart CSR | Frank Chang |
2021-12-20 | target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits | Frank Chang |
2021-12-20 | target/riscv: rvv-1.0: narrowing floating-point/integer type-convert | Frank Chang |
2021-12-20 | target/riscv: rvv-1.0: widening floating-point/integer type-convert | Frank Chang |
2021-12-20 | target/riscv: rvv-1.0: floating-point min/max instructions | Frank Chang |
2021-12-20 | target/riscv: rvv-1.0: remove vmford.vv and vmford.vf | Frank Chang |
2021-12-20 | target/riscv: rvv-1.0: remove widening saturating scaled multiply-add | Frank Chang |