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path: root/target/riscv/translate.c
AgeCommit message (Expand)Author
2023-03-29target/riscv: Set pc_succ_insn for !rvc illegal insnRichard Henderson
2022-09-13target/riscv: Honour -semihosting-config userspace=on and enable=onPeter Maydell
2022-09-07target/riscv: rvv: Add mask agnostic for vv instructionsYueh-Ting (eop) Chen
2022-09-07target/riscv: Fix typo and restore Pointer Masking functionality for RISC-VAlexey Baturo
2022-09-07target/riscv: fix shifts shamt value for rv128cFrédéric Pétrot
2022-09-06target/riscv: Make translator stop before the end of a pageRichard Henderson
2022-09-06target/riscv: Add MAX_INSN_LEN and insn_lenRichard Henderson
2022-09-06accel/tcg: Add pc and host_pc params to gen_intermediate_codeRichard Henderson
2022-07-03target/riscv: Minimize the calls to decode_save_opcRichard Henderson
2022-07-03target/riscv: Remove generate_exception_mtvalRichard Henderson
2022-07-03target/riscv: Set env->bins in gen_exception_illegalRichard Henderson
2022-06-10target/riscv: rvv: Add tail agnostic for vector load / store instructionseopXD
2022-06-10target/riscv: rvv: Add tail agnostic for vv instructionseopXD
2022-05-24target/riscv: Set [m|s]tval for both illegal and virtual instruction trapsAnup Patel
2022-04-29target/riscv: rvk: add support for zknd/zkne extension in RV32Weiwei Li
2022-04-29target/riscv: rvk: add support for zbkb extensionWeiwei Li
2022-04-20exec/translator: Pass the locked filepointer to disas_log hookRichard Henderson
2022-03-03target/riscv: add support for zdinxWeiwei Li
2022-03-03target/riscv: add support for zfinxWeiwei Li
2022-03-03target/riscv: hardwire mstatus.FS to zero when enable zfinxWeiwei Li
2022-02-16target/riscv: add support for svinval extensionWeiwei Li
2022-02-16target/riscv: Add XVentanaCondOps custom extensionPhilipp Tomsich
2022-02-16target/riscv: iterate over a table of decodersPhilipp Tomsich
2022-02-16target/riscv: access configuration through cfg_ptr in DisasContextPhilipp Tomsich
2022-02-16target/riscv: riscv_tr_init_disas_context: copy pointer-to-cfg into cfg_ptrPhilipp Tomsich
2022-01-21target/riscv: Split pm_enabled into mask and baseLIU Zhiwei
2022-01-21target/riscv: Calculate address according to XLENLIU Zhiwei
2022-01-21target/riscv: Alloc tcg global for cur_pm[mask|base]LIU Zhiwei
2022-01-21target/riscv: Sign extend pc for different XLENLIU Zhiwei
2022-01-21target/riscv: Sign extend link reg for jal and jalrLIU Zhiwei
2022-01-21target/riscv: rvv-1.0: Add Zve32f extension into RISC-VFrank Chang
2022-01-21target/riscv: rvv-1.0: Add Zve64f extension into RISC-VFrank Chang
2022-01-08target/riscv: Implement the stval/mtval illegal instructionAlistair Francis
2022-01-08target/riscv: Set the opcode in DisasContextAlistair Francis
2022-01-08target/riscv: support for 128-bit arithmetic instructionsFrédéric Pétrot
2022-01-08target/riscv: support for 128-bit shift instructionsFrédéric Pétrot
2022-01-08target/riscv: support for 128-bit U-type instructionsFrédéric Pétrot
2022-01-08target/riscv: support for 128-bit bitwise instructionsFrédéric Pétrot
2022-01-08target/riscv: accessors to registers upper part and 128-bit load/storeFrédéric Pétrot
2022-01-08target/riscv: array for the 64 upper bits of 128-bit registersFrédéric Pétrot
2022-01-08target/riscv: separation of bitwise logic and arithmetic helpersFrédéric Pétrot
2022-01-08target/riscv: additional macros to check instruction supportFrédéric Pétrot
2021-12-20target/riscv: rvv-1.0: Add ELEN checks for widening and narrowing instructionsFrank Chang
2021-12-20target/riscv: rvv-1.0: implement vstart CSRFrank Chang
2021-12-20target/riscv: add "set round to odd" rounding mode helper functionFrank Chang
2021-12-20target/riscv: rvv-1.0: add fractional LMULFrank Chang
2021-12-20target/riscv: rvv-1.0: remove MLEN calculationsFrank Chang
2021-12-20target/riscv: rvv-1.0: add translation-time vector context statusFrank Chang
2021-12-20target/riscv: zfh: implement zfhmin extensionFrank Chang
2021-12-20target/riscv: zfh: half-precision convert and moveKito Cheng
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