aboutsummaryrefslogtreecommitdiff
path: root/target/riscv/translate.c
AgeCommit message (Expand)Author
2021-10-28target/riscv: Implement address masking functions required for RISC-V Pointer...Anatoly Parshintsev
2021-10-28target/riscv: Support pointer masking for RISC-V for i/c/f/d/a types of instr...Alexey Baturo
2021-10-22target/riscv: Compute mstatus.sd on demandRichard Henderson
2021-10-22target/riscv: Use gen_shift*_per_ol for RVB, RVIRichard Henderson
2021-10-22target/riscv: Use gen_unary_per_ol for RVBRichard Henderson
2021-10-22target/riscv: Use gen_arith_per_ol for RVMRichard Henderson
2021-10-22target/riscv: Replace DisasContext.w with DisasContext.olRichard Henderson
2021-10-22target/riscv: Replace is_32bit with get_xl/get_xlenRichard Henderson
2021-10-22target/riscv: Add MXL/SXL/UXL to TB_FLAGSRichard Henderson
2021-10-22target/riscv: Split misa.mxl and misa.extRichard Henderson
2021-10-22target/riscv: fix TB_FLAGS bits overlapping bug for rvv/rvhFrank Chang
2021-10-15target/riscv: Remove exit_tb and lookup_and_goto_ptrRichard Henderson
2021-10-07target/riscv: Set mstatus_hs.[SD|FS] bits if Clean and V=1 in mark_fs_dirty()Frank Chang
2021-10-07target/riscv: Add a REQUIRE_32BIT macroPhilipp Tomsich
2021-09-14accel/tcg: Add DisasContextBase argument to translator_ld*Ilya Leoshkevich
2021-09-01target/riscv: Use {get,dest}_gpr for RVVRichard Henderson
2021-09-01target/riscv: Use DisasExtend in shift operationsRichard Henderson
2021-09-01target/riscv: Add DisasExtend to gen_unaryRichard Henderson
2021-09-01target/riscv: Move gen_* helpers for RVBRichard Henderson
2021-09-01target/riscv: Move gen_* helpers for RVMRichard Henderson
2021-09-01target/riscv: Remove gen_arith_div*Richard Henderson
2021-09-01target/riscv: Add DisasExtend to gen_arith*Richard Henderson
2021-09-01target/riscv: Introduce DisasExtend and new helpersRichard Henderson
2021-09-01target/riscv: Add DisasContext to gen_get_gpr, gen_set_gprRichard Henderson
2021-09-01target/riscv: Clean up division helpersRichard Henderson
2021-09-01target/riscv: Use tcg_constant_*Richard Henderson
2021-07-21accel/tcg: Remove TranslatorOps.breakpoint_checkRichard Henderson
2021-07-09target/riscv: Use translator_use_goto_tbRichard Henderson
2021-06-24target/riscv: Use target_ulong for the DisasContext misaAlistair Francis
2021-06-08target/riscv: rvb: add/shift with prefix zero-extendKito Cheng
2021-06-08target/riscv: rvb: address calculationKito Cheng
2021-06-08target/riscv: rvb: generalized or-combineFrank Chang
2021-06-08target/riscv: rvb: generalized reverseFrank Chang
2021-06-08target/riscv: rvb: rotate (left/right)Kito Cheng
2021-06-08target/riscv: rvb: shift onesKito Cheng
2021-06-08target/riscv: rvb: single-bit instructionsFrank Chang
2021-06-08target/riscv: add gen_shifti() and gen_shiftiw() helper functionsFrank Chang
2021-06-08target/riscv: rvb: pack two words into one registerKito Cheng
2021-06-08target/riscv: rvb: count bits setFrank Chang
2021-06-08target/riscv: rvb: count leading/trailing zerosKito Cheng
2021-05-11target/riscv: Consolidate RV32/64 32-bit instructionsAlistair Francis
2021-05-11target/riscv: Remove an unused CASE_OP_32_64 macroAlistair Francis
2021-05-11target/riscv: Remove the hardcoded MSTATUS_SD macroAlistair Francis
2021-05-11target/riscv: Remove privilege v1.9 specific CSR related codeAtish Patra
2021-03-22target/riscv: Prevent lost illegal instruction exceptionsGeorg Kotheimer
2021-01-18riscv: Add semihosting supportKeith Packard
2020-11-09target/riscv: Remove the hyp load and store functionsAlistair Francis
2020-08-25target/riscv: Update the Hypervisor trap return/entryAlistair Francis
2020-08-21target/riscv: Check nanboxed inputs in trans_rvf.inc.cRichard Henderson
2020-08-21target/riscv: Generalize gen_nanbox_fpr to gen_nanbox_sRichard Henderson
generated by cgit v1.2.3 (git 2.26.2) at 2025-03-17 06:00:31 +0000