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QEMU is a generic and open source machine & userspace emulator and virtualizer
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translate.c
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2021-10-28
target/riscv: Implement address masking functions required for RISC-V Pointer...
Anatoly Parshintsev
2021-10-28
target/riscv: Support pointer masking for RISC-V for i/c/f/d/a types of instr...
Alexey Baturo
2021-10-22
target/riscv: Compute mstatus.sd on demand
Richard Henderson
2021-10-22
target/riscv: Use gen_shift*_per_ol for RVB, RVI
Richard Henderson
2021-10-22
target/riscv: Use gen_unary_per_ol for RVB
Richard Henderson
2021-10-22
target/riscv: Use gen_arith_per_ol for RVM
Richard Henderson
2021-10-22
target/riscv: Replace DisasContext.w with DisasContext.ol
Richard Henderson
2021-10-22
target/riscv: Replace is_32bit with get_xl/get_xlen
Richard Henderson
2021-10-22
target/riscv: Add MXL/SXL/UXL to TB_FLAGS
Richard Henderson
2021-10-22
target/riscv: Split misa.mxl and misa.ext
Richard Henderson
2021-10-22
target/riscv: fix TB_FLAGS bits overlapping bug for rvv/rvh
Frank Chang
2021-10-15
target/riscv: Remove exit_tb and lookup_and_goto_ptr
Richard Henderson
2021-10-07
target/riscv: Set mstatus_hs.[SD|FS] bits if Clean and V=1 in mark_fs_dirty()
Frank Chang
2021-10-07
target/riscv: Add a REQUIRE_32BIT macro
Philipp Tomsich
2021-09-14
accel/tcg: Add DisasContextBase argument to translator_ld*
Ilya Leoshkevich
2021-09-01
target/riscv: Use {get,dest}_gpr for RVV
Richard Henderson
2021-09-01
target/riscv: Use DisasExtend in shift operations
Richard Henderson
2021-09-01
target/riscv: Add DisasExtend to gen_unary
Richard Henderson
2021-09-01
target/riscv: Move gen_* helpers for RVB
Richard Henderson
2021-09-01
target/riscv: Move gen_* helpers for RVM
Richard Henderson
2021-09-01
target/riscv: Remove gen_arith_div*
Richard Henderson
2021-09-01
target/riscv: Add DisasExtend to gen_arith*
Richard Henderson
2021-09-01
target/riscv: Introduce DisasExtend and new helpers
Richard Henderson
2021-09-01
target/riscv: Add DisasContext to gen_get_gpr, gen_set_gpr
Richard Henderson
2021-09-01
target/riscv: Clean up division helpers
Richard Henderson
2021-09-01
target/riscv: Use tcg_constant_*
Richard Henderson
2021-07-21
accel/tcg: Remove TranslatorOps.breakpoint_check
Richard Henderson
2021-07-09
target/riscv: Use translator_use_goto_tb
Richard Henderson
2021-06-24
target/riscv: Use target_ulong for the DisasContext misa
Alistair Francis
2021-06-08
target/riscv: rvb: add/shift with prefix zero-extend
Kito Cheng
2021-06-08
target/riscv: rvb: address calculation
Kito Cheng
2021-06-08
target/riscv: rvb: generalized or-combine
Frank Chang
2021-06-08
target/riscv: rvb: generalized reverse
Frank Chang
2021-06-08
target/riscv: rvb: rotate (left/right)
Kito Cheng
2021-06-08
target/riscv: rvb: shift ones
Kito Cheng
2021-06-08
target/riscv: rvb: single-bit instructions
Frank Chang
2021-06-08
target/riscv: add gen_shifti() and gen_shiftiw() helper functions
Frank Chang
2021-06-08
target/riscv: rvb: pack two words into one register
Kito Cheng
2021-06-08
target/riscv: rvb: count bits set
Frank Chang
2021-06-08
target/riscv: rvb: count leading/trailing zeros
Kito Cheng
2021-05-11
target/riscv: Consolidate RV32/64 32-bit instructions
Alistair Francis
2021-05-11
target/riscv: Remove an unused CASE_OP_32_64 macro
Alistair Francis
2021-05-11
target/riscv: Remove the hardcoded MSTATUS_SD macro
Alistair Francis
2021-05-11
target/riscv: Remove privilege v1.9 specific CSR related code
Atish Patra
2021-03-22
target/riscv: Prevent lost illegal instruction exceptions
Georg Kotheimer
2021-01-18
riscv: Add semihosting support
Keith Packard
2020-11-09
target/riscv: Remove the hyp load and store functions
Alistair Francis
2020-08-25
target/riscv: Update the Hypervisor trap return/entry
Alistair Francis
2020-08-21
target/riscv: Check nanboxed inputs in trans_rvf.inc.c
Richard Henderson
2020-08-21
target/riscv: Generalize gen_nanbox_fpr to gen_nanbox_s
Richard Henderson
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