slackcoder/qemu - QEMU is a generic and open source machine & userspace emulator and virtualizer

Age	Commit message (Expand)	Author
2024-03-22	target/riscv: rvv: Remove the dependency of Zvfbfmin to Zfbfmin	Max Chou
2024-03-22	target/riscv: do not enable all named features by default	Daniel Henrique Barboza
2024-03-08	target/riscv: Promote svade to a normal extension	Andrew Jones
2024-03-08	target/riscv: Gate hardware A/D PTE bit updating	Andrew Jones
2024-03-08	target/riscv: add remaining named features	Daniel Henrique Barboza
2024-03-08	target/riscv: add riscv,isa to named features	Daniel Henrique Barboza
2024-03-08	target/riscv/tcg: set 'mmu' with 'satp' in cpu_set_profile()	Daniel Henrique Barboza
2024-02-09	target/riscv: Validate misa_mxl_max only once	Akihiko Odaki
2024-02-09	target/riscv: Move misa_mxl_max to class	Akihiko Odaki
2024-02-09	target/riscv: Remove misa_mxl validation	Akihiko Odaki
2024-02-09	target/riscv/cpu.c: remove cpu->cfg.vlen	Daniel Henrique Barboza
2024-02-09	target/riscv: remove riscv_cpu_options[]	Daniel Henrique Barboza
2024-02-09	target/riscv: move 'elen' to riscv_cpu_properties[]	Daniel Henrique Barboza
2024-02-09	target/riscv: move 'vlen' to riscv_cpu_properties[]	Daniel Henrique Barboza
2024-02-09	target/riscv: rework 'vext_spec'	Daniel Henrique Barboza
2024-02-09	target/riscv: rework 'priv_spec'	Daniel Henrique Barboza
2024-02-09	target/riscv: make riscv_cpu_is_vendor() public	Daniel Henrique Barboza
2024-02-09	target/riscv: Add step to validate 'B' extension	Rob Bradford
2024-02-09	target/riscv: Add infrastructure for 'B' MISA extension	Rob Bradford
2024-01-29	include/qemu: Add TCGCPUOps typedef to typedefs.h	Richard Henderson
2024-01-19	target/riscv: Rename tcg_cpu_FOO() to include 'riscv'	Philippe Mathieu-Daudé
2024-01-10	target/riscv: add 'parent' in profile description	Daniel Henrique Barboza
2024-01-10	target/riscv: add satp_mode profile support	Daniel Henrique Barboza
2024-01-10	target/riscv: add priv ver restriction to profiles	Daniel Henrique Barboza
2024-01-10	target/riscv: implement svade	Daniel Henrique Barboza
2024-01-10	target/riscv: add 'rva22u64' CPU	Daniel Henrique Barboza
2024-01-10	target/riscv/tcg: validate profiles during finalize	Daniel Henrique Barboza
2024-01-10	target/riscv/tcg: honor user choice for G MISA bits	Daniel Henrique Barboza
2024-01-10	target/riscv/tcg: add hash table insert helpers	Daniel Henrique Barboza
2024-01-10	target/riscv/tcg: handle profile MISA bits	Daniel Henrique Barboza
2024-01-10	target/riscv/tcg: add riscv_cpu_write_misa_bit()	Daniel Henrique Barboza
2024-01-10	target/riscv/tcg: add MISA user options hash	Daniel Henrique Barboza
2024-01-10	target/riscv/tcg: add user flag for profile support	Daniel Henrique Barboza
2024-01-10	target/riscv/tcg: add 'zic64b' support	Daniel Henrique Barboza
2024-01-10	target/riscv/tcg: update priv_ver on user_set extensions	Daniel Henrique Barboza
2024-01-10	target/riscv/tcg: do not use "!generic" CPU checks	Daniel Henrique Barboza
2024-01-10	target/riscv: Add support for Zacas extension	Weiwei Li
2023-11-22	target/riscv: don't verify ISA compatibility for zicntr and zihpm	Clément Chigot
2023-11-07	target/riscv: Add "pmu-mask" property to replace "pmu-num"	Rob Bradford
2023-11-07	target/riscv: Propagate error from PMU setup	Rob Bradford
2023-11-07	target/riscv: Add cfg properties for Zvks[c\|g] extensions	Max Chou
2023-11-07	target/riscv: Add cfg properties for Zvkn[c\|g] extensions	Max Chou
2023-11-07	target/riscv: Add cfg property for Zvkb extension	Max Chou
2023-11-07	target/riscv: Add cfg property for Zvkt extension	Max Chou
2023-11-07	target/riscv: add zihpm extension flag for TCG	Daniel Henrique Barboza
2023-11-07	target/riscv: add zicntr extension flag for TCG	Daniel Henrique Barboza
2023-11-07	Add epmp to extensions list and rename it to smepmp	Himanshu Chauhan
2023-11-07	target/riscv: add riscv_cpu_accelerator_compatible()	Daniel Henrique Barboza
2023-11-07	target/riscv/tcg: add tcg_cpu_finalize_features()	Daniel Henrique Barboza
2023-11-07	target/riscv: Set VS* bits to one in mideleg when H-Ext is enabled	Rajnesh Kanwal