| Age | Commit message (Expand) | Author |
|---|
| 2023-11-07 | target/riscv: Add "pmu-mask" property to replace "pmu-num" | Rob Bradford |
| 2023-11-07 | target/riscv: Add HS-mode virtual interrupt and IRQ filtering support. | Rajnesh Kanwal |
| 2023-11-07 | target/riscv: Add M-mode virtual interrupt and IRQ filtering support. | Rajnesh Kanwal |
| 2023-06-28 | target/riscv: Restrict KVM-specific fields from ArchCPU | Philippe Mathieu-Daudé |
| 2023-05-05 | target/riscv: Fix format for indentation | Weiwei Li |
| 2023-05-05 | target/riscv: Convert env->virt to a bool env->virt_enabled | LIU Zhiwei |
| 2023-05-05 | target/riscv: add support for Zcmt extension | Weiwei Li |
| 2023-03-01 | target/riscv/cpu: remove CPUArchState::features and friends | Daniel Henrique Barboza |
| 2023-03-01 | target/riscv: remove RISCV_FEATURE_PMP | Daniel Henrique Barboza |
| 2023-03-01 | target/riscv: remove RISCV_FEATURE_DEBUG | Daniel Henrique Barboza |
| 2023-01-20 | hw/char: riscv_htif: Move registers from CPUArchState to HTIFState | Bin Meng |
| 2023-01-06 | target/riscv: Add itrigger_enabled field to CPURISCVState | LIU Zhiwei |
| 2023-01-06 | target/riscv: Add smstateen support | Mayuresh Chitale |
| 2022-09-27 | target/riscv: debug: Introduce tdata1, tdata2, and tdata3 CSRs | Frank Chang |
| 2022-09-27 | target/riscv: debug: Determine the trigger type from tdata1.type | Frank Chang |
| 2022-09-27 | target/riscv: Set the CPU resetvec directly | Alistair Francis |
| 2022-09-07 | target/riscv: Add sscofpmf extension support | Atish Patra |
| 2022-09-07 | target/riscv: Add vstimecmp support | Atish Patra |
| 2022-09-07 | target/riscv: Add stimecmp support | Atish Patra |
| 2022-09-07 | hw/intc: Move mtimer/mtimecmp to aclint | Atish Patra |
| 2022-07-03 | target/riscv: Support mcycle/minstret write operation | Atish Patra |
| 2022-07-03 | target/riscv: Add support for hpmcounters/hpmevents | Atish Patra |
| 2022-07-03 | target/riscv: Implement mcountinhibit CSR | Atish Patra |
| 2022-04-22 | target/riscv: machine: Add debug state description | Bin Meng |
| 2022-04-22 | target/riscv: Add *envcfg* CSRs support | Atish Patra |
| 2022-02-16 | target/riscv: Implement AIA xiselect and xireg CSRs | Anup Patel |
| 2022-02-16 | target/riscv: Implement AIA hvictl and hviprioX CSRs | Anup Patel |
| 2022-02-16 | target/riscv: Implement AIA CSRs for 64 local interrupts on RV32 | Anup Patel |
| 2022-02-16 | target/riscv: Implement AIA local interrupt priorities | Anup Patel |
| 2022-02-16 | target/riscv: Implement hgeie and hgeip CSRs | Anup Patel |
| 2022-01-21 | target/riscv: Split out the vill from vtype | LIU Zhiwei |
| 2022-01-21 | target/riscv: Create current pm fields in env | LIU Zhiwei |
| 2022-01-21 | target/riscv: Create xl field in env | LIU Zhiwei |
| 2022-01-21 | target/riscv: Support virtual time context synchronization | Yifei Jiang |
| 2022-01-08 | target/riscv: adding high part of some csrs | Frédéric Pétrot |
| 2022-01-08 | target/riscv: array for the 64 upper bits of 128-bit registers | Frédéric Pétrot |
| 2021-11-17 | target/riscv: machine: Sort the .subsections | Bin Meng |
| 2021-10-28 | target/riscv: Add J extension state description | Alexey Baturo |
| 2021-10-22 | target/riscv: Split misa.mxl and misa.ext | Richard Henderson |
| 2021-05-11 | target/riscv: Remove privilege v1.9 specific CSR related code | Atish Patra |
| 2020-11-03 | target/riscv: Add V extension state description | Yifei Jiang |
| 2020-11-03 | target/riscv: Add H extension state description | Yifei Jiang |
| 2020-11-03 | target/riscv: Add PMP state description | Yifei Jiang |
| 2020-11-03 | target/riscv: Add basic vmstate description of CPU | Yifei Jiang |
