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AgeCommit message (Expand)Author
2022-01-08target/riscv: moving some insns close to similar insnsFrédéric Pétrot
2022-01-08target/riscv: separation of bitwise logic and arithmetic helpersFrédéric Pétrot
2022-01-08exec/memop: Adding signedness to quad definitionsFrédéric Pétrot
2022-01-08target/riscv: rvv-1.0: Call the correct RVF/RVD check function for narrowing ...Frank Chang
2022-01-08target/riscv: rvv-1.0: Call the correct RVF/RVD check function for widening f...Frank Chang
2022-01-08target/riscv: rvv-1.0: Call the correct RVF/RVD check function for widening f...Frank Chang
2021-12-20target/riscv: rvv-1.0: Add ELEN checks for widening and narrowing instructionsFrank Chang
2021-12-20target/riscv: rvv-1.0: update opivv_vadc_check() commentFrank Chang
2021-12-20target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to vmandn.mm and vmo...Frank Chang
2021-12-20target/riscv: rvv-1.0: add vector unit-stride mask load/store insnsFrank Chang
2021-12-20target/riscv: rvv-1.0: add vsetivli instructionFrank Chang
2021-12-20target/riscv: rvv-1.0: floating-point reciprocal estimate instructionFrank Chang
2021-12-20target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruc...Frank Chang
2021-12-20target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not validFrank Chang
2021-12-20target/riscv: rvv-1.0: implement vstart CSRFrank Chang
2021-12-20target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bitsFrank Chang
2021-12-20target/riscv: rvv-1.0: narrowing floating-point/integer type-convertFrank Chang
2021-12-20target/riscv: rvv-1.0: widening floating-point/integer type-convertFrank Chang
2021-12-20target/riscv: rvv-1.0: floating-point/integer type-convert instructionsFrank Chang
2021-12-20target/riscv: introduce floating-point rounding mode enumFrank Chang
2021-12-20target/riscv: rvv-1.0: remove integer extract instructionFrank Chang
2021-12-20target/riscv: rvv-1.0: remove vmford.vv and vmford.vfFrank Chang
2021-12-20target/riscv: rvv-1.0: remove widening saturating scaled multiply-addFrank Chang
2021-12-20target/riscv: rvv-1.0: single-width scaling shift instructionsFrank Chang
2021-12-20target/riscv: rvv-1.0: widening floating-point reduction instructionsFrank Chang
2021-12-20target/riscv: rvv-1.0: single-width floating-point reductionFrank Chang
2021-12-20target/riscv: rvv-1.0: narrowing fixed-point clip instructionsFrank Chang
2021-12-20target/riscv: rvv-1.0: floating-point slide instructionsFrank Chang
2021-12-20target/riscv: rvv-1.0: mask-register logical instructionsFrank Chang
2021-12-20target/riscv: rvv-1.0: integer comparison instructionsFrank Chang
2021-12-20target/riscv: rvv-1.0: single-width saturating add and subtract instructionsFrank Chang
2021-12-20target/riscv: rvv-1.0: narrowing integer right shift instructionsFrank Chang
2021-12-20target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrowFrank Chang
2021-12-20target/riscv: rvv-1.0: single-width bit shift instructionsFrank Chang
2021-12-20target/riscv: rvv-1.0: single-width averaging add and subtract instructionsFrank Chang
2021-12-20target/riscv: rvv-1.0: integer extension instructionsFrank Chang
2021-12-20target/riscv: rvv-1.0: whole register move instructionsFrank Chang
2021-12-20target/riscv: rvv-1.0: floating-point scalar move instructionsFrank Chang
2021-12-20target/riscv: rvv-1.0: floating-point move instructionFrank Chang
2021-12-20target/riscv: rvv-1.0: integer scalar move instructionsFrank Chang
2021-12-20target/riscv: rvv-1.0: register gather instructionsFrank Chang
2021-12-20target/riscv: rvv-1.0: allow load element with sign-extendedFrank Chang
2021-12-20target/riscv: rvv-1.0: iota instructionFrank Chang
2021-12-20target/riscv: rvv-1.0: set-X-first mask bit instructionsFrank Chang
2021-12-20target/riscv: rvv-1.0: find-first-set mask bit instructionFrank Chang
2021-12-20target/riscv: rvv-1.0: count population in mask instructionFrank Chang
2021-12-20target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculationFrank Chang
2021-12-20target/riscv: rvv-1.0: update vext_max_elems() for load/store insnsFrank Chang
2021-12-20target/riscv: rvv-1.0: load/store whole register instructionsFrank Chang
2021-12-20target/riscv: rvv-1.0: fault-only-first unit stride loadFrank Chang
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