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path: root/target/riscv/insn_trans
AgeCommit message (Expand)Author
2023-11-07target/riscv: Replace Zvbb checking by ZvkbMax Chou
2023-11-07target/riscv: rename ext_icboz to ext_zicbozDaniel Henrique Barboza
2023-11-07target/riscv: rename ext_icbom to ext_zicbomDaniel Henrique Barboza
2023-11-07target/riscv: rename ext_ifencei to ext_zifenceiDaniel Henrique Barboza
2023-10-03tcg: Rename cpu_env to tcg_envRichard Henderson
2023-09-11target/riscv: Fix zfa fleq.d and fltq.dLIU Zhiwei
2023-09-11target/riscv: Add Zvksed ISA extension supportMax Chou
2023-09-11target/riscv: Add Zvkg ISA extension supportNazar Kazakov
2023-09-11target/riscv: Add Zvksh ISA extension supportLawrence Hunter
2023-09-11target/riscv: Add Zvknh ISA extension supportKiran Ostrolenk
2023-09-11target/riscv: Add Zvkned ISA extension supportNazar Kazakov
2023-09-11target/riscv: Add Zvbb ISA extension supportDickon Hood
2023-09-11target/riscv: Refactor translation of vector-widening instructionDickon Hood
2023-09-11target/riscv: Move vector translation checksNazar Kazakov
2023-09-11target/riscv: Add Zvbc ISA extension supportLawrence Hunter
2023-09-11target/riscv: Remove redundant "cpu_vl == 0" checksNazar Kazakov
2023-09-11target/riscv: Refactor vector-vector translation macroKiran Ostrolenk
2023-09-08riscv: spelling fixesMichael Tokarev
2023-07-10riscv: Add support for the Zfa extensionChristoph Müllner
2023-07-10target/riscv: Add support for Zvfbfwma extensionWeiwei Li
2023-07-10target/riscv: Add support for Zvfbfmin extensionWeiwei Li
2023-07-10target/riscv: Add support for Zfbfmin extensionWeiwei Li
2023-06-13target/riscv: Enable PC-relative translationWeiwei Li
2023-06-13target/riscv: Use true diff for gen_pc_plus_diffWeiwei Li
2023-06-13target/riscv: Change gen_set_pc_imm to gen_update_pcWeiwei Li
2023-06-13target/riscv: Change gen_goto_tb to work on displacementsWeiwei Li
2023-06-13target/riscv: Fix target address to update badaddrWeiwei Li
2023-06-13target/riscv: Reuse tb->flags.FSMayuresh Chitale
2023-06-13target/riscv: Update check for Zca/Zcf/ZcdWeiwei Li
2023-06-05accel/tcg: Introduce translator_io_startRichard Henderson
2023-05-05target/riscv: Handle HLV, HSV via helpersRichard Henderson
2023-05-05target/riscv: Reduce overhead of MSTATUS_SUM changeFei Wu
2023-05-05target/riscv: Separate priv from mmu_idxFei Wu
2023-05-05target/riscv: Add a tb flags field for vstartLIU Zhiwei
2023-05-05target/riscv: Encode the FS and VS on a normal way for tb flagsLIU Zhiwei
2023-05-05target/riscv: remove cpu->cfg.ext_eDaniel Henrique Barboza
2023-05-05target/riscv: Fix format for commentsWeiwei Li
2023-05-05target/riscv: Fix format for indentationWeiwei Li
2023-05-05target/riscv: Set opcode to env->bins for illegal/virtual instruction faultWeiwei Li
2023-05-05target/riscv: Fix itrigger when icount is usedLIU Zhiwei
2023-05-05target/riscv: add support for Zcmt extensionWeiwei Li
2023-05-05target/riscv: add support for Zcmp extensionWeiwei Li
2023-05-05target/riscv: add support for Zcb extensionWeiwei Li
2023-05-05target/riscv: add support for Zcd extensionWeiwei Li
2023-05-05target/riscv: add support for Zcf extensionWeiwei Li
2023-05-05target/riscv: add support for Zca extensionWeiwei Li
2023-05-05target/riscv: redirect XVentanaCondOps to use the Zicond functionsPhilipp Tomsich
2023-05-05target/riscv: refactor Zicond supportPhilipp Tomsich
2023-03-07Merge tag 'pull-riscv-to-apply-20230306' of https://gitlab.com/palmer-dabbelt...Peter Maydell
2023-03-05target/riscv: Avoid tcg_const_*Richard Henderson
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