slackcoder/qemu - QEMU is a generic and open source machine & userspace emulator and virtualizer

Age	Commit message (Expand)	Author
2024-06-03	target/riscv: rvv: Remove redudant SEW checking for vector fp narrow/widen in...	Max Chou
2024-06-03	target/riscv: rvv: Check single width operator for vfncvt.rod.f.f.w	Max Chou
2024-06-03	target/riscv: rvv: Check single width operator for vector fp widen instructions	Max Chou
2024-06-03	target/riscv: rvv: Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w ins...	Max Chou
2024-06-03	target/riscv: Add support for Zve32x extension	Jason Chien
2024-03-22	target/riscv: enable 'vstart_eq_zero' in the end of insns	Ivan Klokov
2024-03-22	trans_rvv.c.inc: remove redundant mark_vs_dirty() calls	Daniel Henrique Barboza
2024-03-22	target/riscv: remove 'over' brconds from vector trans	Daniel Henrique Barboza
2024-03-22	target/riscv: always clear vstart for ldst_whole insns	Daniel Henrique Barboza
2024-03-22	target/riscv: always clear vstart in whole vec move insns	Daniel Henrique Barboza
2024-03-22	trans_rvv.c.inc: set vstart = 0 in int scalar move insns	Daniel Henrique Barboza
2024-03-08	trans_rvv.c.inc: remove 'is_store' bool from load/store fns	Daniel Henrique Barboza
2024-03-08	trans_rvv.c.inc: mark_vs_dirty() before loads and stores	Daniel Henrique Barboza
2024-03-08	RISC-V: Add support for Ztso	Palmer Dabbelt
2024-02-09	trans_rvv.c.inc: use vext_get_vlmax() in trans_vrgather_v*()	Daniel Henrique Barboza
2024-02-09	target/riscv/insn_trans/trans_rvv.c.inc: use 'vlenb' in MAXSZ()	Daniel Henrique Barboza
2024-02-09	target/riscv/insn_trans/trans_rvv.c.inc: use 'vlenb'	Daniel Henrique Barboza
2024-01-10	target/riscv: The whole vector register move instructions depend on vsew	Max Chou
2024-01-10	target/riscv: Add vill check for whole vector register move instructions	Max Chou
2023-10-03	tcg: Rename cpu_env to tcg_env	Richard Henderson
2023-09-11	target/riscv: Refactor translation of vector-widening instruction	Dickon Hood
2023-09-11	target/riscv: Move vector translation checks	Nazar Kazakov
2023-09-11	target/riscv: Remove redundant "cpu_vl == 0" checks	Nazar Kazakov
2023-09-11	target/riscv: Refactor vector-vector translation macro	Kiran Ostrolenk
2023-09-08	riscv: spelling fixes	Michael Tokarev
2023-06-13	target/riscv: Change gen_set_pc_imm to gen_update_pc	Weiwei Li
2023-05-05	target/riscv: Add a tb flags field for vstart	LIU Zhiwei
2023-05-05	target/riscv: Encode the FS and VS on a normal way for tb flags	LIU Zhiwei
2023-05-05	target/riscv: Fix format for comments	Weiwei Li
2023-05-05	target/riscv: Fix format for indentation	Weiwei Li
2023-03-05	target/riscv: Avoid tcg_const_*	Richard Henderson
2023-03-05	target/riscv: Drop tcg_temp_free	Richard Henderson
2023-03-01	target/riscv: Simplify check for EEW = 64 in trans_rvv.c.inc	Weiwei Li
2023-03-01	target/riscv: Fix check for vector load/store instructions when EEW=64	Weiwei Li
2023-03-01	target/riscv: Add support for Zvfh/zvfhmin extensions	Weiwei Li
2023-03-01	target/riscv: Remove redundunt check for zve32f and zve64f	Weiwei Li
2023-03-01	target/riscv: Replace check for F/D to Zve32f/Zve64d in trans_rvv.c.inc	Weiwei Li
2023-03-01	target/riscv: Simplify check for Zve32f and Zve64f	Weiwei Li
2023-01-20	target/riscv: Introduce helper_set_rounding_mode_chkfrm	Richard Henderson
2023-01-06	target/riscv: Add itrigger support when icount is not enabled	LIU Zhiwei
2022-09-27	target/riscv: rvv-1.0: vf[w]redsum distinguish between ordered/unordered	Yang Liu
2022-09-07	target/riscv: rvv: Add mask agnostic for vector permutation instructions	Yueh-Ting (eop) Chen
2022-09-07	target/riscv: rvv: Add mask agnostic for vector mask instructions	Yueh-Ting (eop) Chen
2022-09-07	target/riscv: rvv: Add mask agnostic for vector floating-point instructions	Yueh-Ting (eop) Chen
2022-09-07	target/riscv: rvv: Add mask agnostic for vector integer comparison instructions	Yueh-Ting (eop) Chen
2022-09-07	target/riscv: rvv: Add mask agnostic for vector integer shift instructions	Yueh-Ting (eop) Chen
2022-09-07	target/riscv: rvv: Add mask agnostic for vx instructions	Yueh-Ting (eop) Chen
2022-09-07	target/riscv: rvv: Add mask agnostic for vector load / store instructions	Yueh-Ting (eop) Chen
2022-09-07	target/riscv: rvv: Add mask agnostic for vv instructions	Yueh-Ting (eop) Chen
2022-06-10	target/riscv: trans_rvv: Avoid assert for RV32 and e64	Alistair Francis