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path: root/target/riscv/insn_trans/trans_rvm.c.inc
AgeCommit message (Expand)Author
2023-10-03tcg: Rename cpu_env to tcg_envRichard Henderson
2023-03-05target/riscv: Drop tcg_temp_freeRichard Henderson
2022-06-10target/riscv: add support for zmmul extension v0.1Weiwei Li
2022-01-08target/riscv: support for 128-bit M extensionFrédéric Pétrot
2022-01-08target/riscv: support for 128-bit arithmetic instructionsFrédéric Pétrot
2021-10-22target/riscv: Use gen_arith_per_ol for RVMRichard Henderson
2021-10-22target/riscv: Replace DisasContext.w with DisasContext.olRichard Henderson
2021-09-01target/riscv: Move gen_* helpers for RVMRichard Henderson
2021-09-01target/riscv: Use gen_arith for mulh and mulhuRichard Henderson
2021-09-01target/riscv: Remove gen_arith_div*Richard Henderson
2021-09-01target/riscv: Add DisasExtend to gen_arith*Richard Henderson
2021-09-01target/riscv: Add DisasContext to gen_get_gpr, gen_set_gprRichard Henderson
2021-05-11target/riscv: Consolidate RV32/64 32-bit instructionsAlistair Francis
2020-08-21meson: rename included C source files to .c.incPaolo Bonzini