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QEMU is a generic and open source machine & userspace emulator and virtualizer
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riscv
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insn_trans
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trans_rvf.c.inc
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Commit message (
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Author
2023-10-03
tcg: Rename cpu_env to tcg_env
Richard Henderson
2023-09-08
riscv: spelling fixes
Michael Tokarev
2023-06-13
target/riscv: Reuse tb->flags.FS
Mayuresh Chitale
2023-06-13
target/riscv: Update check for Zca/Zcf/Zcd
Weiwei Li
2023-05-05
target/riscv: Encode the FS and VS on a normal way for tb flags
LIU Zhiwei
2023-05-05
target/riscv: add support for Zcf extension
Weiwei Li
2023-03-05
target/riscv: Drop tcg_temp_free
Richard Henderson
2023-02-07
target/riscv: Ensure opcode is saved for all relevant instructions
Anup Patel
2022-03-03
target/riscv: add support for zfinx
Weiwei Li
2022-01-21
target/riscv: Calculate address according to XLEN
LIU Zhiwei
2021-10-28
target/riscv: Support pointer masking for RISC-V for i/c/f/d/a types of instr...
Alexey Baturo
2021-09-01
target/riscv: Use {get,dest}_gpr for RVF
Richard Henderson
2021-09-01
target/riscv: Add DisasContext to gen_get_gpr, gen_set_gpr
Richard Henderson
2021-09-01
target/riscv: Use tcg_constant_*
Richard Henderson
2021-05-11
target/riscv: Consolidate RV32/64 32-bit instructions
Alistair Francis
2020-08-21
target/riscv: check before allocating TCG temps
LIU Zhiwei
2020-08-21
target/riscv: Clean up fmv.w.x
LIU Zhiwei
2020-08-21
target/riscv: Check nanboxed inputs in trans_rvf.inc.c
Richard Henderson
2020-08-21
target/riscv: Generate nanboxed results from trans_rvf.inc.c
Richard Henderson
2020-08-21
target/riscv: Generalize gen_nanbox_fpr to gen_nanbox_s
Richard Henderson
2020-08-21
meson: rename included C source files to .c.inc
Paolo Bonzini