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path: root/target/riscv/insn_trans/trans_rvb.c.inc
AgeCommit message (Expand)Author
2023-03-05target/riscv: Drop tcg_temp_freeRichard Henderson
2023-02-07target/riscv: fix ctzw behaviorVladimir Isaev
2022-04-29target/riscv: rvk: add support for zbkx extensionWeiwei Li
2022-04-29target/riscv: rvk: add support for zbkc extensionWeiwei Li
2022-04-29target/riscv: rvk: add support for zbkb extensionWeiwei Li
2022-03-03target/riscv: fix inverted checks for ext_zb[abcs]Philipp Tomsich
2022-02-16target/riscv: access cfg structure through DisasContextPhilipp Tomsich
2022-01-08target/riscv: support for 128-bit arithmetic instructionsFrédéric Pétrot
2022-01-08target/riscv: support for 128-bit shift instructionsFrédéric Pétrot
2022-01-08target/riscv: separation of bitwise logic and arithmetic helpersFrédéric Pétrot
2021-10-22target/riscv: Use gen_shift*_per_ol for RVB, RVIRichard Henderson
2021-10-22target/riscv: Use gen_unary_per_ol for RVBRichard Henderson
2021-10-22target/riscv: Adjust trans_rev8_32 for riscv64Richard Henderson
2021-10-22target/riscv: Replace DisasContext.w with DisasContext.olRichard Henderson
2021-10-22target/riscv: Fix orc.b implementationPhilipp Tomsich
2021-10-07target/riscv: Add zext.h instructions to Zbb, removing pack/packu/packhPhilipp Tomsich
2021-10-07target/riscv: Add rev8 instruction, removing grev/greviPhilipp Tomsich
2021-10-07target/riscv: Add orc.b instruction for Zbb, removing gorc/gorciPhilipp Tomsich
2021-10-07target/riscv: Reassign instructions to the Zbb-extensionPhilipp Tomsich
2021-10-07target/riscv: Add instructions of the Zbc-extensionPhilipp Tomsich
2021-10-07target/riscv: Reassign instructions to the Zbs-extensionPhilipp Tomsich
2021-10-07target/riscv: Remove shift-one instructions (proposed Zbo in pre-0.93 draft-B)Philipp Tomsich
2021-10-07target/riscv: Remove the W-form instructions from ZbsPhilipp Tomsich
2021-10-07target/riscv: Reassign instructions to the Zba-extensionPhilipp Tomsich
2021-10-07target/riscv: clwz must ignore high bits (use shift-left & changed logic)Philipp Tomsich
2021-10-07target/riscv: fix clzw implementation to operate on arg1Philipp Tomsich
2021-10-07target/riscv: Introduce temporary in gen_add_uw()Philipp Tomsich
2021-09-01target/riscv: Use gen_shift_imm_fn for slli_uwRichard Henderson
2021-09-01target/riscv: Use DisasExtend in shift operationsRichard Henderson
2021-09-01target/riscv: Add DisasExtend to gen_unaryRichard Henderson
2021-09-01target/riscv: Move gen_* helpers for RVBRichard Henderson
2021-09-01target/riscv: Add DisasExtend to gen_arith*Richard Henderson
2021-09-01target/riscv: Add DisasContext to gen_get_gpr, gen_set_gprRichard Henderson
2021-06-08target/riscv: rvb: add/shift with prefix zero-extendKito Cheng
2021-06-08target/riscv: rvb: address calculationKito Cheng
2021-06-08target/riscv: rvb: generalized or-combineFrank Chang
2021-06-08target/riscv: rvb: generalized reverseFrank Chang
2021-06-08target/riscv: rvb: rotate (left/right)Kito Cheng
2021-06-08target/riscv: rvb: shift onesKito Cheng
2021-06-08target/riscv: rvb: single-bit instructionsFrank Chang
2021-06-08target/riscv: rvb: sign-extend instructionsKito Cheng
2021-06-08target/riscv: rvb: min/max instructionsKito Cheng
2021-06-08target/riscv: rvb: pack two words into one registerKito Cheng
2021-06-08target/riscv: rvb: logic-with-negateKito Cheng
2021-06-08target/riscv: rvb: count bits setFrank Chang
2021-06-08target/riscv: rvb: count leading/trailing zerosKito Cheng
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