aboutsummaryrefslogtreecommitdiff
path: root/target/riscv/insn_trans/trans_rva.c.inc
AgeCommit message (Expand)Author
2024-07-18target/riscv: Move gen_amo before implement ZabhaLIU Zhiwei
2024-07-18target/riscv: Support Zama16b extensionLIU Zhiwei
2024-03-08RISC-V: Add support for ZtsoPalmer Dabbelt
2024-02-09target/riscv: Check 'A' and split extensions for atomic instructionsRob Bradford
2024-02-09target/riscv: Check for 'A' extension on all atomic instructionsRob Bradford
2023-02-07target/riscv: Ensure opcode is saved for all relevant instructionsAnup Patel
2022-01-21target/riscv: Calculate address according to XLENLIU Zhiwei
2022-01-08exec/memop: Adding signedness to quad definitionsFrédéric Pétrot
2021-10-28target/riscv: Support pointer masking for RISC-V for i/c/f/d/a types of instr...Alexey Baturo
2021-09-01target/riscv: Use {get,dest}_gpr for RVARichard Henderson
2021-09-01target/riscv: Add DisasContext to gen_get_gpr, gen_set_gprRichard Henderson
2021-05-11target/riscv: Consolidate RV32/64 32-bit instructionsAlistair Francis
2020-08-21meson: rename included C source files to .c.incPaolo Bonzini