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path: root/target/riscv/insn_trans/trans_privileged.c.inc
AgeCommit message (Expand)Author
2024-06-03trans_privileged.c.inc: set (m|s)tval on ebreak breakpointDaniel Henrique Barboza
2023-10-03tcg: Rename cpu_env to tcg_envRichard Henderson
2023-06-13target/riscv: Change gen_set_pc_imm to gen_update_pcWeiwei Li
2023-06-05accel/tcg: Introduce translator_io_startRichard Henderson
2023-05-05target/riscv: Separate priv from mmu_idxFei Wu
2023-05-05target/riscv: Fix itrigger when icount is usedLIU Zhiwei
2023-01-06target/riscv: Add itrigger support when icount is not enabledLIU Zhiwei
2022-09-13target/riscv: Honour -semihosting-config userspace=on and enable=onPeter Maydell
2022-07-03target/riscv: Minimize the calls to decode_save_opcRichard Henderson
2022-01-21target/riscv: Sign extend pc for different XLENLIU Zhiwei
2022-01-21target/riscv: Don't save pc when exception returnLIU Zhiwei
2021-10-15target/riscv: Remove exit_tb and lookup_and_goto_ptrRichard Henderson
2021-10-15target/riscv: Remove dead code after exceptionRichard Henderson
2021-01-18riscv: Add semihosting supportKeith Packard
2020-08-21meson: rename included C source files to .c.incPaolo Bonzini