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QEMU is a generic and open source machine & userspace emulator and virtualizer
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riscv
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insn16.decode
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Commit message (
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Author
2024-07-18
target/riscv: Add zcmop extension
LIU Zhiwei
2023-05-05
target/riscv: add support for Zcmt extension
Weiwei Li
2023-05-05
target/riscv: add support for Zcmp extension
Weiwei Li
2023-05-05
target/riscv: add support for Zcb extension
Weiwei Li
2023-05-05
target/riscv: add support for Zcd extension
Weiwei Li
2023-05-05
target/riscv: add support for Zcf extension
Weiwei Li
2022-09-07
target/riscv: fix shifts shamt value for rv128c
Frédéric Pétrot
2022-01-08
target/riscv: accessors to registers upper part and 128-bit load/store
Frédéric Pétrot
2021-05-11
target/riscv: Consolidate RV32/64 16-bit instructions
Alistair Francis
2019-05-24
target/riscv: Add checks for several RVC reserved operands
Richard Henderson
2019-05-24
target/riscv: Split RVC32 and RVC64 insns into separate files
Richard Henderson
2019-05-24
target/riscv: Use pattern groups in insn16.decode
Richard Henderson
2019-05-24
target/riscv: Merge argument decode for RVC shifti
Richard Henderson
2019-05-24
target/riscv: Merge argument sets for insn32 and insn16
Richard Henderson
2019-03-13
target/riscv: Convert quadrant 2 of RVXC insns to decodetree
Bastian Koppelmann
2019-03-13
target/riscv: Convert quadrant 1 of RVXC insns to decodetree
Bastian Koppelmann
2019-03-13
target/riscv: Convert quadrant 0 of RVXC insns to decodetree
Bastian Koppelmann