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path: root/target/riscv/insn16.decode
AgeCommit message (Expand)Author
2024-07-18target/riscv: Add zcmop extensionLIU Zhiwei
2023-05-05target/riscv: add support for Zcmt extensionWeiwei Li
2023-05-05target/riscv: add support for Zcmp extensionWeiwei Li
2023-05-05target/riscv: add support for Zcb extensionWeiwei Li
2023-05-05target/riscv: add support for Zcd extensionWeiwei Li
2023-05-05target/riscv: add support for Zcf extensionWeiwei Li
2022-09-07target/riscv: fix shifts shamt value for rv128cFrédéric Pétrot
2022-01-08target/riscv: accessors to registers upper part and 128-bit load/storeFrédéric Pétrot
2021-05-11target/riscv: Consolidate RV32/64 16-bit instructionsAlistair Francis
2019-05-24target/riscv: Add checks for several RVC reserved operandsRichard Henderson
2019-05-24target/riscv: Split RVC32 and RVC64 insns into separate filesRichard Henderson
2019-05-24target/riscv: Use pattern groups in insn16.decodeRichard Henderson
2019-05-24target/riscv: Merge argument decode for RVC shiftiRichard Henderson
2019-05-24target/riscv: Merge argument sets for insn32 and insn16Richard Henderson
2019-03-13target/riscv: Convert quadrant 2 of RVXC insns to decodetreeBastian Koppelmann
2019-03-13target/riscv: Convert quadrant 1 of RVXC insns to decodetreeBastian Koppelmann
2019-03-13target/riscv: Convert quadrant 0 of RVXC insns to decodetreeBastian Koppelmann