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path: root/target/riscv/debug.h
AgeCommit message (Expand)Author
2024-10-02target/riscv: Add textra matching condition for the triggersAlvin Chang
2024-04-26exec: Declare CPUBreakpoint/CPUWatchpoint type in 'breakpoint.h' headerPhilippe Mathieu-Daudé
2023-09-11target/riscv: Allocate itrigger timers only onceAkihiko Odaki
2023-01-06target/riscv: Add itrigger support when icount is enabledLIU Zhiwei
2023-01-06target/riscv: Add itrigger support when icount is not enabledLIU Zhiwei
2022-09-27target/riscv: debug: Add initial support of type 6 triggerFrank Chang
2022-09-27target/riscv: debug: Create common trigger actions functionFrank Chang
2022-09-27target/riscv: debug: Introduce tinfo CSRFrank Chang
2022-09-27target/riscv: debug: Introduce tdata1, tdata2, and tdata3 CSRsFrank Chang
2022-09-27target/riscv: debug: Introduce build_tdata1() to build tdata1 register contentFrank Chang
2022-09-27target/riscv: debug: Determine the trigger type from tdata1.typeFrank Chang
2022-04-22target/riscv: csr: Hook debug CSR read/writeBin Meng
2022-04-22target/riscv: debug: Implement debug related TCGCPUOpsBin Meng
2022-04-22target/riscv: Add initial support for the Sdtrig extensionBin Meng