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QEMU is a generic and open source machine & userspace emulator and virtualizer
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riscv
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debug.h
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2024-10-02
target/riscv: Add textra matching condition for the triggers
Alvin Chang
2024-04-26
exec: Declare CPUBreakpoint/CPUWatchpoint type in 'breakpoint.h' header
Philippe Mathieu-Daudé
2023-09-11
target/riscv: Allocate itrigger timers only once
Akihiko Odaki
2023-01-06
target/riscv: Add itrigger support when icount is enabled
LIU Zhiwei
2023-01-06
target/riscv: Add itrigger support when icount is not enabled
LIU Zhiwei
2022-09-27
target/riscv: debug: Add initial support of type 6 trigger
Frank Chang
2022-09-27
target/riscv: debug: Create common trigger actions function
Frank Chang
2022-09-27
target/riscv: debug: Introduce tinfo CSR
Frank Chang
2022-09-27
target/riscv: debug: Introduce tdata1, tdata2, and tdata3 CSRs
Frank Chang
2022-09-27
target/riscv: debug: Introduce build_tdata1() to build tdata1 register content
Frank Chang
2022-09-27
target/riscv: debug: Determine the trigger type from tdata1.type
Frank Chang
2022-04-22
target/riscv: csr: Hook debug CSR read/write
Bin Meng
2022-04-22
target/riscv: debug: Implement debug related TCGCPUOps
Bin Meng
2022-04-22
target/riscv: Add initial support for the Sdtrig extension
Bin Meng