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path: root/target/riscv/csr.c
AgeCommit message (Expand)Author
2021-10-22target/riscv: Add MXL/SXL/UXL to TB_FLAGSRichard Henderson
2021-10-22target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxlRichard Henderson
2021-10-22target/riscv: Split misa.mxl and misa.extRichard Henderson
2021-09-21target/riscv: csr: Rename HCOUNTEREN_CY and friendsBin Meng
2021-09-21target/riscv: Fix satp writeLIU Zhiwei
2021-09-01target/riscv: Fix hgeie, hgeipRichard Henderson
2021-09-01target/riscv: Fix rmw_sip, rmw_vsip, rmw_hsip vs write-only operationRichard Henderson
2021-09-01target/riscv: Add User CSRs read-only checkLIU Zhiwei
2021-09-01target/riscv: Correct a comment in riscv_csrrw()Bin Meng
2021-07-15target/riscv: hardwire bits in hideleg and hedelegJose Martins
2021-07-15target/riscv: csr: Remove redundant check in fp csr read/write routinesBin Meng
2021-05-11target/riscv: Remove the hardcoded SATP_MODE macroAlistair Francis
2021-05-11target/riscv: Remove the hardcoded MSTATUS_SD macroAlistair Francis
2021-05-11target/riscv: Remove the hardcoded SSTATUS_SD macroAlistair Francis
2021-05-11target/riscv: Add ePMP CSR access functionsHou Weiying
2021-05-11target/riscv: Use RISCVException enum for CSR accessAlistair Francis
2021-05-11target/riscv: Use the RISCVException enum for CSR operationsAlistair Francis
2021-05-11target/riscv: Fix 32-bit HS mode access permissionsAlistair Francis
2021-05-11target/riscv: Use the RISCVException enum for CSR predicatesAlistair Francis
2021-05-11target/riscv: Remove privilege v1.9 specific CSR related codeAtish Patra
2021-03-22target/riscv: Fix read and write accesses to vsip and vsieGeorg Kotheimer
2021-03-22target/riscv: Make VSTIP and VSEIP read-only in hipGeorg Kotheimer
2021-03-22target/riscv: fix vs() to return proper error codeFrank Chang
2021-01-16target/riscv: Add CSR name in the CSR function tableBin Meng
2021-01-16target/riscv: Make csr_ops[CSR_TABLE_SIZE] externalBin Meng
2020-12-17target/riscv: csr: Remove compile time XLEN checksAlistair Francis
2020-11-03target/riscv/csr.c : add space before the open parenthesis '('Xinhao Zhang
2020-11-03target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unitYifei Jiang
2020-10-05icount: rename functions to be consistent with the module nameClaudio Fontana
2020-10-05cpu-timers, icount: new modulesClaudio Fontana
2020-09-09hw/riscv: clint: Avoid using hard-coded timebase frequencyBin Meng
2020-08-25target/riscv: Support the Virtual Instruction faultAlistair Francis
2020-08-25target/riscv: Return the exception from invalid CSR accessesAlistair Francis
2020-08-25target/riscv: Support the v0.6 Hypervisor extension CRSsAlistair Francis
2020-08-25target/riscv: Only support little endian guestsAlistair Francis
2020-08-25target/riscv: Only support a single VSXL lengthAlistair Francis
2020-08-25target/riscv: Convert MSTATUS MTL to GVAAlistair Francis
2020-08-25target/riscv: Don't allow guest to write to htinstAlistair Francis
2020-07-22target/riscv: Fix the range of pmpcfg of CSR funcion tableZong Li
2020-07-02target/riscv: support vector extension csrLIU Zhiwei
2020-06-03target/riscv: Drop support for ISA spec version 1.09.1Alistair Francis
2020-02-27target/riscv: Emulate TIME CSRs for privileged modeAnup Patel
2020-02-27target/riscv: Add support for the 32-bit MSTATUSH CSRAlistair Francis
2020-02-27target/riscv: Extend the SIP CSR to support virtulisationAlistair Francis
2020-02-27target/riscv: Extend the MIE CSR to support virtulisationAlistair Francis
2020-02-27target/riscv: Set VS bits in mideleg for Hyp extensionAlistair Francis
2020-02-27target/riscv: Add Hypervisor machine CSRs accessesAlistair Francis
2020-02-27target/riscv: Add Hypervisor virtual CSRs accessesAlistair Francis
2020-02-27target/riscv: Add Hypervisor CSR access functionsAlistair Francis
2020-02-27target/riscv: Fix CSR perm checking for HS modeAlistair Francis
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