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path: root/target/riscv/csr.c
AgeCommit message (Expand)Author
2024-01-08target/riscv: Fix mcycle/minstret increment behaviorXu Lu
2023-11-07target/riscv: Don't assume PMU counters are continuousRob Bradford
2023-11-07target/riscv: correct csr_ops[CSR_MSECCFG]Heinrich Schuchardt
2023-11-07target/riscv: add zicntr extension flag for TCGDaniel Henrique Barboza
2023-11-07Add epmp to extensions list and rename it to smepmpHimanshu Chauhan
2023-11-07target/riscv: Add HS-mode virtual interrupt and IRQ filtering support.Rajnesh Kanwal
2023-11-07target/riscv: Add M-mode virtual interrupt and IRQ filtering support.Rajnesh Kanwal
2023-11-07target/riscv: Without H-mode mask all HS mode inturrupts in mie.Rajnesh Kanwal
2023-11-07target/riscv: rename ext_icsr to ext_zicsrDaniel Henrique Barboza
2023-10-12target/riscv: move riscv_cpu_validate_set_extensions() to tcg-cpu.cDaniel Henrique Barboza
2023-09-11target/riscv: don't read CSR in riscv_csrrw_do64Nikita Shubin
2023-09-11target/riscv: Align the AIA model to v1.0 ratified specTommy Wu
2023-09-11target/riscv: Update CSR bits name for svadu extensionWeiwei Li
2023-09-11target/riscv: Implement WARL behaviour for mcountinhibit/mcounterenRob Bradford
2023-09-08riscv: spelling fixesMichael Tokarev
2023-08-31target/helpers: Remove unnecessary 'qemu/main-loop.h' headerPhilippe Mathieu-Daudé
2023-07-10target/riscv: update cur_pmbase/pmmask based on mode affected by MPRVWeiwei Li
2023-07-10target/riscv: Remove redundant assignment to SXLWeiwei Li
2023-07-10target/riscv: Support MSTATUS.MPV/GVA only when RVH is enabledWeiwei Li
2023-06-13target/riscv: smstateen check for fcsrMayuresh Chitale
2023-06-13target/riscv: Update cur_pmmask/base when xl changesWeiwei Li
2023-06-13target/riscv: rework write_misa()Daniel Henrique Barboza
2023-05-05target/riscv: Restore the predicate() NULL check behaviorBin Meng
2023-05-05target/riscv: Set MMU_2STAGE_BIT in riscv_cpu_mmu_indexRichard Henderson
2023-05-05target/riscv: Reduce overhead of MSTATUS_SUM changeFei Wu
2023-05-05target/riscv: Add a general status enum for extensionsLIU Zhiwei
2023-05-05target/riscv: fix H extension TVM trapYi Chen
2023-05-05target/riscv: Legalize MPP value in write_mstatusWeiwei Li
2023-05-05target/riscv: Fix lines with over 80 charactersWeiwei Li
2023-05-05target/riscv: Fix format for commentsWeiwei Li
2023-05-05target/riscv: Remove riscv_cpu_virt_enabled()Weiwei Li
2023-05-05target/riscv: add support for Zcmt extensionWeiwei Li
2023-05-05target/riscv: Simplify arguments for riscv_csrrw_checkWeiwei Li
2023-05-05target/riscv: Simplify type conversion for CPURISCVStateWeiwei Li
2023-05-05target/riscv: Avoid env_archcpu() when reading RISCVCPUConfigWeiwei Li
2023-03-07includes: move tb_flush into its own headerAlex Bennée
2023-03-06riscv: Allow user to set the satp modeAlexandre Ghiti
2023-03-06riscv: Change type of valid_vm_1_10_[32|64] to boolAlexandre Ghiti
2023-03-01Merge patch series "RISCVCPUConfig related cleanups"Palmer Dabbelt
2023-03-01target/riscv/csr.c: avoid env_archcpu() usages when reading RISCVCPUConfigDaniel Henrique Barboza
2023-03-01target/riscv/csr.c: use riscv_cpu_cfg() to avoid env_cpu() pointersDaniel Henrique Barboza
2023-03-01target/riscv/csr.c: simplify mctr()Daniel Henrique Barboza
2023-03-01target/riscv/csr.c: use env_archcpu() in ctr()Daniel Henrique Barboza
2023-03-01Merge patch series "target/riscv: Add support for Svadu extension"Palmer Dabbelt
2023-03-01target/riscv: Add csr support for svaduWeiwei Li
2023-03-01target/riscv: Fix the relationship of PBMTE/STCE fields between menvcfg and h...Weiwei Li
2023-03-01target/riscv: Fix the relationship between menvcfg.PBMTE/STCE and Svpbmt/Sstc...Weiwei Li
2023-03-01Merge patch series "target/riscv: Various fixes to gdbstub and CSR access"Palmer Dabbelt
2023-03-01target/riscv: Group all predicate() routines togetherBin Meng
2023-03-01target/riscv: Drop priv level check in mseccfg predicate()Bin Meng
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