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path: root/target/riscv/csr.c
AgeCommit message (Expand)Author
2023-07-10target/riscv: update cur_pmbase/pmmask based on mode affected by MPRVWeiwei Li
2023-07-10target/riscv: Remove redundant assignment to SXLWeiwei Li
2023-07-10target/riscv: Support MSTATUS.MPV/GVA only when RVH is enabledWeiwei Li
2023-06-13target/riscv: smstateen check for fcsrMayuresh Chitale
2023-06-13target/riscv: Update cur_pmmask/base when xl changesWeiwei Li
2023-06-13target/riscv: rework write_misa()Daniel Henrique Barboza
2023-05-05target/riscv: Restore the predicate() NULL check behaviorBin Meng
2023-05-05target/riscv: Set MMU_2STAGE_BIT in riscv_cpu_mmu_indexRichard Henderson
2023-05-05target/riscv: Reduce overhead of MSTATUS_SUM changeFei Wu
2023-05-05target/riscv: Add a general status enum for extensionsLIU Zhiwei
2023-05-05target/riscv: fix H extension TVM trapYi Chen
2023-05-05target/riscv: Legalize MPP value in write_mstatusWeiwei Li
2023-05-05target/riscv: Fix lines with over 80 charactersWeiwei Li
2023-05-05target/riscv: Fix format for commentsWeiwei Li
2023-05-05target/riscv: Remove riscv_cpu_virt_enabled()Weiwei Li
2023-05-05target/riscv: add support for Zcmt extensionWeiwei Li
2023-05-05target/riscv: Simplify arguments for riscv_csrrw_checkWeiwei Li
2023-05-05target/riscv: Simplify type conversion for CPURISCVStateWeiwei Li
2023-05-05target/riscv: Avoid env_archcpu() when reading RISCVCPUConfigWeiwei Li
2023-03-07includes: move tb_flush into its own headerAlex Bennée
2023-03-06riscv: Allow user to set the satp modeAlexandre Ghiti
2023-03-06riscv: Change type of valid_vm_1_10_[32|64] to boolAlexandre Ghiti
2023-03-01Merge patch series "RISCVCPUConfig related cleanups"Palmer Dabbelt
2023-03-01target/riscv/csr.c: avoid env_archcpu() usages when reading RISCVCPUConfigDaniel Henrique Barboza
2023-03-01target/riscv/csr.c: use riscv_cpu_cfg() to avoid env_cpu() pointersDaniel Henrique Barboza
2023-03-01target/riscv/csr.c: simplify mctr()Daniel Henrique Barboza
2023-03-01target/riscv/csr.c: use env_archcpu() in ctr()Daniel Henrique Barboza
2023-03-01Merge patch series "target/riscv: Add support for Svadu extension"Palmer Dabbelt
2023-03-01target/riscv: Add csr support for svaduWeiwei Li
2023-03-01target/riscv: Fix the relationship of PBMTE/STCE fields between menvcfg and h...Weiwei Li
2023-03-01target/riscv: Fix the relationship between menvcfg.PBMTE/STCE and Svpbmt/Sstc...Weiwei Li
2023-03-01Merge patch series "target/riscv: Various fixes to gdbstub and CSR access"Palmer Dabbelt
2023-03-01target/riscv: Group all predicate() routines togetherBin Meng
2023-03-01target/riscv: Drop priv level check in mseccfg predicate()Bin Meng
2023-03-01target/riscv: Allow debugger to access sstc CSRsBin Meng
2023-03-01target/riscv: Allow debugger to access {h, s}stateen CSRsBin Meng
2023-03-01target/riscv: Allow debugger to access seed CSRBin Meng
2023-03-01target/riscv: Allow debugger to access user timer and counter CSRsBin Meng
2023-03-01target/riscv: Avoid reporting odd-numbered pmpcfgX in the CSR XML for RV64Bin Meng
2023-03-01target/riscv: Simplify getting RISCVCPU pointer from envBin Meng
2023-03-01target/riscv: Simplify {read, write}_pmpcfg() a little bitBin Meng
2023-03-01target/riscv: Use 'bool' type for read_onlyBin Meng
2023-03-01target/riscv: Coding style fixes in csr.cBin Meng
2023-03-01target/riscv: Use g_assert() for the predicate() NULL checkBin Meng
2023-03-01target/riscv: Add some comments to clarify the priority policy of riscv_csrrw...Bin Meng
2023-03-01Merge patch series "target/riscv: Some updates to float point related extensi...Palmer Dabbelt
2023-03-01target/riscv: Simplify check for Zve32f and Zve64fWeiwei Li
2023-03-01target/riscv: remove RISCV_FEATURE_MMUDaniel Henrique Barboza
2023-03-01target/riscv: remove RISCV_FEATURE_PMPDaniel Henrique Barboza
2023-03-01target/riscv: remove RISCV_FEATURE_EPMPDaniel Henrique Barboza
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